This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the filtering effect of CMOS-gates avoids superfluous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a delay balanced circuit are the same as the transition densities calculated with a zero delay model. Guaranteeing a transition density as calculated with a zero delay model makes logic decomposition and technology mapping for low power much easier and makes the much used zero delay model assumption in logic decomposition and technology mapping for low power more valid. In this paper we formulate the gate sizing problem for gate sizing for minimal power while removing glitches. We take into account both dynamic power dissipation as well as short-circuit power dissipation. To remove glitches we introduce additional constraints. We discuss the merits of the formulation and the problems encountered ...

As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multi-source wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for single-source wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous single-source wire sizing methods in practice.

Abstract. The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a v ¯ ariable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called v ¯ ariable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1

Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimum-allowed gate size. This problem is well known to be a geometric program (GP), and can be solved by using standard interiorpoint methods for small- and medium-size problems with up to several thousand gates. In this paper, we describe a new method for solving this problem that handles far larger circuits, up to a million gates, and is far faster. Numerical experiments show that our method can compute an adequately accurate solution within around 200 iterations; each iteration, in turn, consists of a few passes over the circuit. In particular, the complexity of our method, with a fixed number of iterations, is linear in the number of gates. A simple implementation of our algorithm can size a 10 000 gate circuit in 25 s, a 100 000 gate circuit in 4 min, and a million gate circuit in 40 min, approximately. For the million gate circuit, the associated GP has three million variables and more than six million monomial terms in its constraints; as far as we know, these are the largest GPs ever solved. Index Terms—Gate sizing, geometric programming (GP), largescale optimization. I.

A gate that offers different delays for different input-output paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by a path balancing and glitch filtering techniques discussed in recent publications. In this paper, we describe transistor sizing methods for three types of VID gates that satisfy given delay requirements. The three ways to obtain the differential delays are capacitance manipulation, nMOS transistor insertion, and CMOS transmission gate insertion. We also describe techniques for calculating the ub of each VID gate type. Finally, we outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1

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