Programmable processors offer a high degree of flexibility and are therefore increasingly being used in embedded systems. We introduce the formalism nML which is especially suited to describe such processors in terms of their instruction set, an nML description is directly related to the standard description as found in the usual programmer's manuals. The nML formalism is based on a mixed structural and behavioural model facilitating exact yet concise descriptions. The philosophy of nML is already applied in two approaches to retargetable code generation and instruction set simulation. 1 Introduction In consumer electronics and telecommunications high product volumes are increasingly combined with short life-times and high system complexity. The pressure on development times together with the demand to react on late specification changes make mask or field programmability a desired feature. The thereby obtained flexibility not only helps to shorten the design cycle, but also allows fo...

nML is a formalism targetted for describing arbitrary single-processor computer architectures. nML works at the instruction set level, i.e. it hides implementation issues of the actual machine. nML can be used as an input language for a wide range of tools that need formal machine descriptions. Based on attribute grammars, nML is flexible and reasonably easy to use. Contents 1 Introduction 2 1.1 Where are Machine Descriptions needed? : : : : : : : : : : : : : : : : : : : : : : : : 2 1.2 Different Kinds of Machine Descriptions : : : : : : : : : : : : : : : : : : : : : : : : : 2 1.2.1 GCC's .md format : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 2 1.2.2 The VHDL Hardware Definition Language : : : : : : : : : : : : : : : : : : : 3 1.3 General aims of nML : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 4 1.3.1 Abstraction Level : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 4 1.3.2 Sharing in Descriptions : : : : : : :...

This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors (DSPs) using the modeling language LISA. In the past, the principle of compiled simulation as means for speeding up simulators has only been implemented for specific DSP architectures. The new approach presented here discusses methods of integrating compiled simulation techniques to retargetable simulation tools. The principle and the implementation are discussed in this paper and results for the TI TMS320C6201 DSP are presented.

When developing software for embedded systems, the set of essential tools includes a compiler and an instruction set simulator. Since software and hardware are often designed in parallel, the tools must be easily adaptable to the changing target architecture. For the compiler, its back-end (the code generator) must be retargetable. Abstraction from the target machine is the key to an automated approach. Additionally, abstraction from tool-internal strategies permits the utilization of a unified machine description for all tools. In this chapter, the machine description formalism nML is presented along with the retargetable code generator Cbc and the instruction set simulation environment Sigh/Sim. 1 INTRODUCTION For the realization of retargetable software development tools such as a code generator and an instruction set simulator, several aspects of the potential target machines must be modeled in an abstract manner. These machine models are necessary to formalize the tool's methods...

. We describe a novel technique for code selection based on data-flow graphs, which arise naturally in the domain of digital signal processing. Code selection is the optimized mapping of abstract operations to partial machine instructions. The presented method performs an important task within the retargetable microcode generator CBC, which was designed to cope with the requirements arising in the context of custom digital signal processor (DSP) programming. The algorithm exploits a graph representation in which control-flow is modeled by scopes. 1 Introduction In the domain of medium-throughput digital signal processing, micro-programmable processor cores are frequently chosen for system realization. By adding dedicated hardware (accelerator paths), these cores are tailored to the needs of new applications. Optimized processor modules can be reused, which is a major benefit compared to high-level synthesis [28] where a completely new design is developed for each application. ...

Efficient embedded DSP system design requires methods of hardware/software codesign. In this contribution we focus on software synthesis for partitioned system behavioral descriptions. In previous approaches, this task is performed by compiling the behavioral descriptions onto standard processors using target-specific compilers. It is argued that abandoning this restriction allows for higher degrees of freedom in design space exploration. In turn, this demands for retargetable code generation tools. We present different schemes for DSP code generation using the MSSQ microcode generator. Experiments with industrial applications revealed that retargetable DSP code generation based on structural hardware descriptions is feasible, but there exists a strong dependency between the behavioral description style and the resulting code quality. As a result, necessary features of high-quality retargetable DSP code generators are identified. 1 1 INTRODUCTION Embedded systems in general comprise ...

This paper presents a methodology to automatically generate production quality software development tools for programmable architectures using the machine description language LISA. Various architectures presenting diverse architectural originalities will be presented and the feasibility of automatically generating simulator, assembler, linker and graphical debugger frontend will be discussed. The presented approach is not limited to a fixed abstraction level -- case studies of the Texas Instruments C62x and C54x, the Analog Devices ADSP2101 as well as the ARM7 will show the applicability of the methodology from cycle/phase to instruction accurate models.

Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hardware implementation. For this reason, design parameters such as timing, area or power consumption cannot be taken into consideration accurately during design space exploration. Design automation tools currently used to bridge this gap are either limited in the flexibility provided or only generate fragments of the architecture. This paper presents a synthesis tool which preserves the full flexibility of the architecture description language LISA, while being able to generate the complete architecture on RT-level using SystemC. This paper also presents two real world architecture case studies to prove the feasibility of our approach. 1

The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Several software generation tools have been developed that take ISA specifications in Sim-nML as input. In this paper we present a tool Sim-HS that implements high level behavioral and structural synthesis of processors from their ISA specifications in Sim-nML. Behavioral Sim-HS transforms Sim-nML specifications of a processor to the corresponding behavioral Verilog model that is suitable for fast functional simulation. Structural Sim-HS generates structural synthesizable Verilog processor model from its Sim-nML specifications. 1

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