Results 1  10
of
28
Firstorder incremental blockbased statistical timing analysis
 In DAC
, 2004
"... Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel lineartime blockbased statistical timing algorithm is emplo ..."
Abstract

Cited by 125 (4 self)
 Add to MetaCart
Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel lineartime blockbased statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. The statistical timing analysis is incremental, and is therefore suitable for use in the inner loop of physical synthesis or other optimization programs. The second novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the timing graph being critical is computed. These criticality probabilities provide additional useful diagnostics to synthesis, optimization, test generation and path enumeration programs. Numerical results are presented on industrial ASIC chips with over two million logic gates. 1.
Death, Taxes and Failing Chips
, 2003
"... In the way they cope with variability, presentday methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for firsttimeright hardware and cuttinged ..."
Abstract

Cited by 50 (3 self)
 Add to MetaCart
In the way they cope with variability, presentday methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for firsttimeright hardware and cuttingedge performance. This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem. These aspects of the problem are compared and contrasted in the ASIC and custom (microprocessor) domains. This paper pays particular attention to statistical timing analysis and enumerates desirable attributes that would render such an analysis capability practical and accurate.
Statistical Timing Analysis Under Spatial Correlations
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2005
"... Abstract — Process variations are of increasing concern in today’s technologies, and can significantly affect circuit performance. We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both interdie and intradie va ..."
Abstract

Cited by 41 (4 self)
 Add to MetaCart
Abstract — Process variations are of increasing concern in today’s technologies, and can significantly affect circuit performance. We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both interdie and intradie variations, while accounting for the effects of spatial correlations of intradie parameter variations. The procedure uses a firstorder Taylor series expansion to approximate the gate and interconnect delays. Next, principal component analysis techniques are��and ��� are employed to transform the set of correlated parameters into an uncorrelated set. The statistical timing computation is then easily performed with a PERTlike circuit graph traversal. The runtime of our algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations. The accuracy of the method is verified with Monte Carlo simulation. On average, for 100nm technology, the errors of mean and standard deviation values computed by the proposed method respectively, and the errors of predicting the��and confidence point are ���and ���respectively. A testcase with about 17,800 gates was solved in about�seconds, with high accuracy as compared to a Monte Carlo simulation that required more than�hours.
Gate Sizing Using Incremental Parameterized Statistical Timing Analysis
 In ICCAD
, 2005
"... Abstract — As technology scales into the sub90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical ..."
Abstract

Cited by 25 (1 self)
 Add to MetaCart
Abstract — As technology scales into the sub90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as statistical distributions during both analysis and optimization. This paper uses incremental, parametric statistical static timing analysis (SSTA) to perform gate sizing with a required yield target. Both correlated and uncorrelated process parameters are considered by using a firstorder linear delay model with fitted process sensitivities. The fitted sensitivities are verified to be accurate with circuit simulations. Statistical information in the form of criticality probabilities are used to actively guide the optimization process which reduces runtime and improves area and performance. The gate sizing results show a significant improvement in worst slack at 99.86 % yield over deterministic optimization. I.
Defining statistical sensitivity for timing optimization of logic circuits with largescale process and environmental variations,” Docket MC06172004P, Filed with the US Patent Office
, 2005
"... The largescale process and environmental variations for today’s nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how o ..."
Abstract

Cited by 20 (3 self)
 Add to MetaCart
The largescale process and environmental variations for today’s nanoscale ICs are requiring statistical approaches for timing analysis and optimization. Significant research has been recently focused on developing new statistical timing analysis algorithms, but often without consideration for how one should interpret the statistical timing results for optimization. In this paper [1] we demonstrate why the traditional concepts of slack and critical path become ineffective under largescale variations, and we propose a novel sensitivitybased metric to assess the “criticality ” of each path and/or arc in the statistical timing graph. We define the statistical sensitivities for both paths and arcs, and theoretically prove that our path sensitivity is equivalent to the probability that a path is critical, and our arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples. 1.
Fast buffer insertion considering process variations
 in Proc. Int. Symp. on Physical Design, 2006
"... A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point out, for the first time, that the correlation between the required arrival time and the downstream loading capacitance must ..."
Abstract

Cited by 12 (1 self)
 Add to MetaCart
A comprehensive probabilistic methodology is proposed to solve the buffer insertion problem with the consideration of process variations. In contrast to a recent work, we point out, for the first time, that the correlation between the required arrival time and the downstream loading capacitance must be considered in order to solve the problem “correctly”. We develop an efficient bottomup recursive algorithm to calculate the joint probability density function that accurately captures the above correlation, and propose effective pruning rules to exclude probabilistically inferior solutions. We verify our buffer insertion using timing analysis with both device and interconnect variations, and show that compared to the conventional buffer insertion algorithm using nominal device and interconnect parameters, our new buffer insertion methodology can reduce the probability of timing violation by up to 30%. 1.
A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing
 IEEE Transactions on Circuits and SystemsI
, 2004
"... A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is th ..."
Abstract

Cited by 12 (4 self)
 Add to MetaCart
A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis. This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN optimization problem is much more difficult; the few existing methods cannot handle largescale problems.
A lineartime approach for static timing analysis covering all process corners
 In ICCAD
, 2006
"... Abstract—Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process corners (combinations of process parameter extremes) to make sure that circuit timing constraints are met at all corners, t ..."
Abstract

Cited by 12 (6 self)
 Add to MetaCart
Abstract—Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process corners (combinations of process parameter extremes) to make sure that circuit timing constraints are met at all corners, typically by running static timing analysis (STA) at every corner. This approach is becoming too expensive due to the increase in the number of corners with modern processes. As an alternative, we propose a lineartime approach for STA which covers all process corners in a single pass. Our technique assumes a linear dependence of delays and slews on process parameters and provides estimates of the worst case circuit delay and slew. It exhibits high accuracy in practice, and if the circuit has m gates and n relevant process parameters, the complexity of the algorithm is O(mn). Index Terms—Hyperplanes, multicorner, process variations, static timing analysis (STA).
Statistical timing analysis with twosided constraints
 In IEEE/ACM International Conference on Computer Aided Design
, 2005
"... ..."
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic
 CMP Variation and Random Leff Variation,” Proceedings of the ACM International Symposium on Physical Design
, 2005
"... This paper studies the impacts of Chemical Mechanical Polishing (CMP)induced systematic variation and random channel length (Leff) variation of transistors on interconnect design. We first construct a table lookup based interconnect RC parasitic model considering CMP effects with optimized fill in ..."
Abstract

Cited by 9 (3 self)
 Add to MetaCart
This paper studies the impacts of Chemical Mechanical Polishing (CMP)induced systematic variation and random channel length (Leff) variation of transistors on interconnect design. We first construct a table lookup based interconnect RC parasitic model considering CMP effects with optimized fill insertion. Based on the model, we solve the simultaneous buffer insertion, wire sizing and fill insertion (SBW F) problem under CMP variation. We also extend the SBW F problem to consider the random Leff variation (vSBW F). We approach the resulting vSBW F problem by (1) incorporating probability density function (PDF) into the SBW F algorithm; and (2) developing an efficient heuristic for PDF pruning, whose practical optimality is verified by an accurate but much slower pruning. Experimental results show that the SBW F design improves timing by 1.0 % and reduces power by 5.7 % on average with 7.4 % less buffer area over the conventional buffer insertion and wire sizing design followed by fill insertion (SBW + F ill), and that the vSBW F design reduces yield loss due to CMP and Leff variations by 44.3 % on average over the SBW + F ill design. The runtime of vSBW F is 8.3 × that of SBW F, and vSBW F for the largest example containing 3103 sinks finishes in 124 minutes.