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27
ªLowComplexity Bitparallel Canonical and Normal Basis Multipliers for a Class of Finite Fields,º
 IEEE Trans. Computers
, 1998
"... Abstract—We present a new lowcomplexity bitparallel canonical basis multiplier for the field GF(2 m) generated by an allonepolynomial. The proposed canonical basis multiplier requires m 2 1 XOR gates and m 2 AND gates. We also extend this canonical basis multiplier to obtain a new bitparallel n ..."
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Cited by 43 (8 self)
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Abstract—We present a new lowcomplexity bitparallel canonical basis multiplier for the field GF(2 m) generated by an allonepolynomial. The proposed canonical basis multiplier requires m 2 1 XOR gates and m 2 AND gates. We also extend this canonical basis multiplier to obtain a new bitparallel normal basis multiplier. Index Terms—Finite fields, multiplication, normal basis, canonical basis, allonepolynomial. 1
A New Architecture for a Parallel Finite Field Multiplier with Low Complexity on Composite Fields
 IEEE Transactions on Computers
, 1996
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FPGA Implementation of Point Multiplication on Koblitz Curves using Kleinian Integers
 In Cryptographic Hardware and Embedded Systems, CHES 2006
, 2006
"... Abstract. We describe algorithms for point multiplication on Koblitz curves using multiplebase expansions of the form k = ∑ ±τ a (τ − 1) b and k = ∑ ±τ a (τ − 1) b (τ 2 − τ − 1) c. We prove that the number of terms in the second type is sublinear in the bit length of k, which leads to the first p ..."
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Cited by 14 (5 self)
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Abstract. We describe algorithms for point multiplication on Koblitz curves using multiplebase expansions of the form k = ∑ ±τ a (τ − 1) b and k = ∑ ±τ a (τ − 1) b (τ 2 − τ − 1) c. We prove that the number of terms in the second type is sublinear in the bit length of k, which leads to the first provably sublinear point multiplication algorithm on Koblitz curves. For the first type, we conjecture that the number of terms is sublinear and provide numerical evidence demonstrating that the number of terms is significantly less than that of τadic nonadjacent form expansions. We present details of an innovative FPGA implementation of our algorithm and performance data demonstrating the efficiency of our method. 1
Efficient Computation of Multiplicative Inverse for Cryptographic Applications
 Proceeding of the 15th IEEE Symposium on Computer Arithmetic
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Customizable elliptic curve cryptosystems
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2005
"... Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiplebit s ..."
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Cited by 13 (1 self)
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Abstract—This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field qp@P A, using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiplebit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets userdefined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster
Normal Bases over Finite Fields
, 1993
"... Interest in normal bases over finite fields stems both from mathematical theory and practical applications. There has been a lot of literature dealing with various properties of normal bases (for finite fields and for Galois extension of arbitrary fields). The advantage of using normal bases to repr ..."
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Cited by 12 (0 self)
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Interest in normal bases over finite fields stems both from mathematical theory and practical applications. There has been a lot of literature dealing with various properties of normal bases (for finite fields and for Galois extension of arbitrary fields). The advantage of using normal bases to represent finite fields was noted by Hensel in 1888. With the introduction of optimal normal bases, large finite fields, that can be used in secure and e#cient implementation of several cryptosystems, have recently been realized in hardware. The present thesis studies various theoretical and practical aspects of normal bases in finite fields. We first give some characterizations of normal bases. Then by using linear algebra, we prove that F q n has a basis over F q such that any element in F q represented in this basis generates a normal basis if and only if some groups of coordinates are not simultaneously zero. We show how to construct an irreducible polynomial of degree 2 n with linearly i...
Vlsi Architecture For Datapath Integration Of Arithmetic Over GF(2^m) On Digital Signal Processors
 in Proc. IEEE ICASSP'97
, 1997
"... This paper examines the implementation of Finite Field arithmetic, i.e. multiplication, division, and exponentiation, for any standard basis GF(2 ) with m8 on a DSP datapath. We introduce an opportunity to exploit cells and the interconnection structure of a typical binary multiplier unit for the ..."
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Cited by 9 (4 self)
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This paper examines the implementation of Finite Field arithmetic, i.e. multiplication, division, and exponentiation, for any standard basis GF(2 ) with m8 on a DSP datapath. We introduce an opportunity to exploit cells and the interconnection structure of a typical binary multiplier unit for the Finite Field operations by adding just a small overhead of logic. We develop division and exponentiation based on multiplication on the algorithm level and present a simple scheme for implementation of all operations on a processor datapath.
A New Algorithm for Multiplication in Finite Fields
 I E E E Trans. Computers
, 1989
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On Parallelization of HighSpeed Processors for Elliptic Curve Cryptography
 IEEE Transaction on Very Large
"... permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Helsinki University of Technology's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or pr ..."
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Cited by 6 (2 self)
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permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Helsinki University of Technology's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubspermissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
B.: “Error control coding in software radios: an FPGA approach
 IEEE Personal Communications
, 1999
"... Among the various tasks performcd by sofhvarc radios is thc reconfiguration of the error control coding algorithm to match the requirement of the radio personality. In the digital radio processor, proper assignment of tasks between DSPs and FPGAs provides perfornuncc improvements over the nsc of DSP ..."
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Cited by 6 (1 self)
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Among the various tasks performcd by sofhvarc radios is thc reconfiguration of the error control coding algorithm to match the requirement of the radio personality. In the digital radio processor, proper assignment of tasks between DSPs and FPGAs provides perfornuncc improvements over the nsc of DSPs alone. Error control coding functions are good candidates to reside on the PPGA side of this ftinctiiinal partition. Unfortunately, good VLSI designs for codes using BCH or ReedSolomon codes do not map well to FPGAs. Good FPGA designs must parallelizc at every opportunity, minimize timing delays through intelligcnt floor planning, and IISC each logic block LO its fullcst. We dcmonstrate thc merits of these concepts by comparing the performance of popular finite field multiplier designs.