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51
The Propositional Formula Checker HeerHugo
 JOURNAL OF AUTOMATED REASONING
, 1999
"... HeerHugo is a propositional formula checker that determines whether a given formula is satisfiable or not. Its main ingredient is the branch/merge rule, that is inspired by an algorithm proposed by Stallmarck, which is protected by a software patent. The algorithm can be interpreted as a breadth f ..."
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Cited by 41 (0 self)
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HeerHugo is a propositional formula checker that determines whether a given formula is satisfiable or not. Its main ingredient is the branch/merge rule, that is inspired by an algorithm proposed by Stallmarck, which is protected by a software patent. The algorithm can be interpreted as a breadth first search algorithm. HeerHugo differs substantially from Stallmarck's algorithm, as it operates on formulas in conjunctive normal form and it is enhanced with many logical rules including unit resolution, 2satisfiability tests and additional systematic reasoning techniques. In this paper, the main elements of the algorithm are discussed, and its remarkable effectiveness is illustrated with some examples and computational results.
Using SAT for Combinational Equivalence Checking
, 2001
"... This paper addresses the problem of combinational equivalence checking (CEC) which forms one of the key components of the current verification methodology for digital systems. A number of recently proposed BDD based approaches have met with considerable success in this area. However, the growing gap ..."
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Cited by 37 (3 self)
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This paper addresses the problem of combinational equivalence checking (CEC) which forms one of the key components of the current verification methodology for digital systems. A number of recently proposed BDD based approaches have met with considerable success in this area. However, the growing gap between the capability of current solvers and the complexity of verification instances necessitates the exploration of alternative, better solutions. This paper revisits the application of Satisfiability (SAT) algorithms to the combinational equivalence checking (CEC) problem. We argue that SAT is a more robust and flexible engine of Boolean reasoning for the CEC application than BDDs, which have traditionally been the method of choice. Preliminary results on a simple framework for SAT based CEC show a speedup of up to two orders of magnitude compared to stateoftheart SAT based methods for CEC and also demonstrate that even with this simple algorithm and untuned prototype implementation it is only moderately slower and sometimes faster than a stateoftheart BDD based mixed engine commercial CEC tool. While SAT based CEC methods need further research and tuning before they can surpass almost a decade of research in BDD based CEC, the recent progress is very promising and merits continued research.
Faster SAT and Smaller BDDs via Common Function Structure
 University of Michigan
, 2001
"... The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worstcase, the structure of realworld instances is a natural source of improvements. While SAT and BDD techn ..."
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Cited by 27 (7 self)
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The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speedups. Since typical SAT and BDD algorithms are exponential in the worstcase, the structure of realworld instances is a natural source of improvements. While SAT and BDD techniques are often presented as mutually exclusive alternatives, our work points out that both can be improved via the use of the same structural properties of instances. Our proposed methods are based on efficient problem partitioning and can be easily applied as preprocessing with arbitrary SAT solvers and BDD packages without source code modifications. Finding a better variableordering is a well recognized problem for both SAT solvers and BDD packages. Currently, all leading edge variableordering algorithms are dynamic, in the sense that they are invoked many times in the course of the “host ” algorithm that solves SAT or manipulates BDDs. Examples include the DLCS ordering for SAT solvers and variablesifting during BDD manipulations. In this work we propose a universal variableordering MINCE (MIN Cut Etc.) that preprocesses a given Boolean formula in CNF. MINCE is completely independent from target algorithms and outperforms both DLCS for SAT and variable sifting for BDDs. We argue that MINCE tends to capture structural properties of Boolean functions arising from realworld applications. Our contribution is validated on the ISCAS circuits and the DIMACS benchmarks. Empirically, our technique often outperforms existing techniques by a factor of two or more. Our results motivate search for stronger dynamic ordering heuristics and combined static/dynamic techniques. 3 1
Exploiting the Real Power of Unit Propagation Lookahead
, 2001
"... One of the best SAT solvers for random 3SAT formulae, SATZ, is based on a heuristic called unit propagation lookahead (UPL). Unfortunately, it does not perform so well on specific structured instances, especially on the ones coming from an area where a huge interest for SAT has emerged in rece ..."
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Cited by 26 (1 self)
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One of the best SAT solvers for random 3SAT formulae, SATZ, is based on a heuristic called unit propagation lookahead (UPL). Unfortunately, it does not perform so well on specific structured instances, especially on the ones coming from an area where a huge interest for SAT has emerged in recent years: symbolic model checking (SMC). We claim that all the power of this heuristic is not used in SATZ, and that UPL can be extended to solve some real world structured problems, where the major competitors are using intelligent backtracking or specific deduction rules. We introduce a preprocessing technique that can be applied to simplify instances containing equivalent literals. This technique is based on UPL, so it can be easily added to any solver using this heuristic. We compare our approach to the new extension of SATZ for equivalency reasoning (EqSATZ) and another approach, the St almarck method, which is mainly used in SMC.
Embedded Languages for Describing and Verifying Hardware
, 2001
"... Abstract Lava is a system for designing, specifying, verifying and implementing hardware. It is embedded in the functional programming language Haskell, which means that hardware descriptions are firstclass objects in Haskell. We are thus able to use modern programming language features, such as hi ..."
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Cited by 23 (2 self)
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Abstract Lava is a system for designing, specifying, verifying and implementing hardware. It is embedded in the functional programming language Haskell, which means that hardware descriptions are firstclass objects in Haskell. We are thus able to use modern programming language features, such as higherorder functions, polymorphism, type classes and laziness, in hardware descriptions. We present two rather different versions of Lava. One version realises the embedding by using monads to keep track of the information specified in a hardware description. The other version uses a new language construct, called observable sharing, which eliminates the need for monads so that descriptions are much cleaner. Adding observable sharing to Haskell is a nonconservative extension, meaning that some properties of Haskell are lost. We thus investigate to what extent we are still allowed to use a normal Haskell compiler or interpreter. We also introduce an embedded language for specifying properties. The use of this language is twofold. On the one hand, we can use it to specify and later formally verify properties of the described circuits. On the other hand, we can use it to specify and randomly test properties of normal Haskell programs. As a bonus, since hardware descriptions are embedded in Haskell, we can also use it to test our circuit descriptions.
Qubos: Deciding Quantified Boolean Logic using Propositional Satisfiability Solvers
 In Proc. 4 th Intl. Conf. on Formal Methods in ComputerAided Design (FMCAD’02), volume 2517 of LNCS
, 2002
"... We describe Qubos (QUantified BOolean Solver), a decision procedure for quantified Boolean logic. The procedure is based on nonclausal simplification techniques that reduce formulae to a propositional clausal form after which o#theshelf satisfiability solvers can be employed. We show that ther ..."
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Cited by 23 (0 self)
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We describe Qubos (QUantified BOolean Solver), a decision procedure for quantified Boolean logic. The procedure is based on nonclausal simplification techniques that reduce formulae to a propositional clausal form after which o#theshelf satisfiability solvers can be employed. We show that there are domains exhibiting structure for which this procedure is very e#ective and we report on experimental results.
Algebraic Simplification Techniques for Propositional Satisfiability
, 2000
"... The ability to reduce either the number of variables or clauses in instances of the Satisfiability problem (SAT) impacts the expected computational effort of solving a given instance. This ability can actually be essential for specific and hard classes of instances. The objective of this paper is to ..."
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Cited by 19 (4 self)
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The ability to reduce either the number of variables or clauses in instances of the Satisfiability problem (SAT) impacts the expected computational effort of solving a given instance. This ability can actually be essential for specific and hard classes of instances. The objective of this paper is to propose new simplification techniques for Conjunctive Normal Form (CNF) formulas. Experimental results, obtained on representative problem instances, indicate that large simplifications can be observed.
Stalmarck's algorithm as a HOL derived rule
 Verlag LNCS 1125
, 1996
"... Abstract. St˚almarck’s algorithm is a patented technique for tautologychecking which has been used successfully for industrialscale problems. Here we describe the algorithm and explore its implementation as a HOL derived rule. 1 ..."
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Cited by 17 (0 self)
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Abstract. St˚almarck’s algorithm is a patented technique for tautologychecking which has been used successfully for industrialscale problems. Here we describe the algorithm and explore its implementation as a HOL derived rule. 1
A Proof Engine Approach to Solving Combinational Design Automation Problems
, 2002
"... There are many approaches available for solving combinational design automation problems encoded as tautology or satisfiability checks. Unfortunately there exists no single analysis that gives adequate performance for all problems of interest, and it is therefore critical to be able to combine appro ..."
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Cited by 14 (1 self)
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There are many approaches available for solving combinational design automation problems encoded as tautology or satisfiability checks. Unfortunately there exists no single analysis that gives adequate performance for all problems of interest, and it is therefore critical to be able to combine approaches.
Efficient Latch Optimization Using Exclusive Sets
, 1997
"... Controller circuits synthesized from highlevel languages often have many more latches than the minimum, with a resulting sparse reachable state space that has a particular structure. We propose an algorithm that exploits this structure to remove latches. The reachable state set (RSS) is much e ..."
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Cited by 14 (5 self)
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Controller circuits synthesized from highlevel languages often have many more latches than the minimum, with a resulting sparse reachable state space that has a particular structure. We propose an algorithm that exploits this structure to remove latches. The reachable state set (RSS) is much easier to compute for the new, smaller circuit and can be used to efficiently compute the RSS of the original. Thus we provide a method for obtaining the RSS, and two different initial implementations from which to begin logic optimization. 1 Introduction The computation of the reachable state set (RSS) of a sequential circuit is important for verification, logic optimization and test generation. The RSS computation is typically done incrementally, by looping over a computation of the next states as the image of the current states by a vector of Boolean functions [3]. When BDDbased algorithms are used, the variables are the latches and the circuit inputs. Therefore, the number of latch...