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A stabilization technique is presented that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay cell, obviating the need for resistors in the loop filter. A 2.4-GHz CMOS frequency synthesizer employing the technique settles in approximately 60 ps with 1-MHz channel spacing while exhibiting a sideband magnitude of-58.7 dBc. Designed for Bluetooth applications and fabricated in a 0.25-

This paper describes a 2-GHz single-chip 0.25-µm CMOS receiver for WCDMA applications. The receiver is based on a direct-conversion architecture and implements all RF components, including the low-noise amplifier, frequency synthesizer, and mixers. The receiver also integrates all baseband components along the in-phase and quadrature signal paths, each of which includes a first-order high-pass filter, a second-order Sallen and Key low-pass filter, and a 7-bit, 25-MS/s Σ∆ analog-to-digital converter operating at 200 MHz. The receiver prototype achieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mW. 1.

The increasing demand for small-form-factor, wireless devices motivates research on highly-integrated, low-cost transmitters [1]. This work describes techniques that potentially allow implementation of the transmitter at higher levels of integration than previously achieved. A prototype CMOS IC for a narrow-band PCS system operating at 1.75GHz includes two baseband signal paths, an image/harmonicrejection upconversion mixer, a channel-selection IF synthesizer, a fixed-frequency RF synthesizer, and two quadrature generation circuits (Figure 10.4.1). The baseband signal path consists of two 10b resistor-string DACs and two 3rd-order Sallen & Key low-pass filters. Delivering required levels of output power, minimizing spurious emissions, and maintaining modulation accuracy are difficult challenges associated with integration of all transmitter functionality onto a single silicon substrate. Direct-upconversion transmitters, while simplifying the signal path, suffer from local oscillator pulling and the challenge

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Abstract—A stabilization technique is presented that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay cell, obviating the need for resistors in the loop filter. A 2.4-GHz CMOS frequency synthesizer employing the technique settles in approximately 60 s with 1-MHz channel spacing while exhibiting a sideband magnitude of 58.7 dBc. Designed for Bluetooth applications and fabricated in a 0.25- m digital CMOS technology, the synthesizer achieves a phase noise of 112 dBc/Hz at 1-MHz offset and consumes 20 mW from a 2.5-V supply. Index Terms—Charge pumps, feedforward, loop stability, oscillators, phase-locked loops (PLLs), prescalers, synthesizers.

The design of a 32/33 frequency divider, that can operate with input frequency up to 3GHz is discussed. The circuit is realized in a 0.351m CMOS technology. Particular attention is devoted to assess, in simple terms, the output phase noise and its reduction due to the adoption of a synchronization flip-flop. The measured noise level, -172 dBc/Hz, matches within ldB with the value predicted by the theory. The minimum input differential signal is 50 mV zero-peak. The power dissipation is 27roW.

RF CMOS Class C Power Amplifiers for Wireless Communications by Ramakrishna Sekhar Narayanaswami Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences University of California, Berkeley Abstract 2 order in order to generate an approximate solution to the design goal before a circuit analysis tool is required. Circuit techniques used to combat the technology limitations imposed by CMOS technologies include the use of differential circuits in the signal path, cascoded stages and a modified tuning method which allowed for the use of extremely large output devices but not requiring passive devices that were not feasible in a CMOS technology.

Abstract—This paper describes the design and implementation of a 2-GHz single-chip 0.25-µm CMOS receiver for a custom WCDMA system. A system-level simulation framework is used to explore the trade-offs between analog front-end impairments and system performance. System specifications are chosen in order to facilitate a low-power highly-integrated implementation. The receiver is based on a direct-conversion architecture and implements all RF components, including the low-noise amplifier, frequency synthesizer, and mixers. The receiver also integrates all baseband components along the in-phase and quadrature signal paths, each of which includes a first-order high-pass filter, a second-order Sallen and Key low-pass filter, and a 7-bit, 25-MS/s Σ ∆ analog-to-digital converter operating at 200 MHz. The receiver prototype achieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mW. I.