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61
Equivalent Elmore Delay for RLC Trees
 Proceedings of the ACM/IEEE Design Automation Conference
, 2000
"... Abstract—Closedform solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore delay for trees and preserves the simplicity and recursive characteristics of the Elmore delay. Specif ..."
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Cited by 37 (8 self)
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Abstract—Closedform solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore delay for trees and preserves the simplicity and recursive characteristics of the Elmore delay. Specifically, the complexity of calculating the time domain responses at all the nodes of an tree is linearly proportional to the number of branches in the tree and the solutions are always stable. The closedform expressions introduced here consider all damping conditions of an circuit including the underdamped response, which is not considered by the Elmore delay due to the nonmonotone nature of the response. The continuous analytical nature of the solutions makes these expressions suitable for design methodologies and optimization techniques. Also, the solutions have significantly improved accuracy as compared to the Elmore delay for an overdamped response. The solutions introduced here for trees can be practically used for the same purposes that the Elmore delay is used for trees.
Reducing Clock Skew Variability via Cross Links
 IN PROCEEDINGS OF THE 41ST ANNUAL CONFERENCE ON DESIGN AUTOMATION
, 2004
"... Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular ..."
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Cited by 30 (8 self)
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Increasingly significant variational e#ects present a great challenge for delivering desired clock skew reliably. Nontree clock network has been recognized as a promising approach to overcome the variation problem. Existing nontree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wires. In this paper, we suggest to construct a low cost nontree clock network by inserting cross links in a given clock tree. The e#ect of the link insertion on clock skew variability is analyzed. Based on the analysis, two link insertion schemes are proposed. These methods can quickly convert a clock tree to a nontree with significantly lower skew variability and very small amount of extra wires. Further, they can be applied to the recently popular nonzero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2% increase of wirelength.
A static patternindependent technique for power grid voltage integrity verification
 Proceedings of the ACM/IEEE Design Automation Conference
, 2003
"... Design verification must include the power grid. Checking that the voltage on the power grid does not drop by more than some critical threshold is a very difficult problem, for at least two reasons: i) the obviously large size of the power grids for modern highperformance chips, and ii) the difficu ..."
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Cited by 30 (10 self)
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Design verification must include the power grid. Checking that the voltage on the power grid does not drop by more than some critical threshold is a very difficult problem, for at least two reasons: i) the obviously large size of the power grids for modern highperformance chips, and ii) the difficulty of setting up the right simulation conditions for the power grid that provide some measure of a realistic worst case voltage drop. The huge number of possible circuit operational modes or workloads makes it impossible to do exhaustive analysis. We propose a static technique for power grid verification, where static is in the sense of static timing analysis, meaning that it does not depend on, nor require, userspecified stimulus to drive a simulation. The verification is posed as an optimization problem under usersupplied current constraints. We propose that current constraints are the right kind of abstraction to use in order to develop a practical methodology for power grid verification. We present our verification approach, and report on the results of applying it to a number of testcase power grids.
Congestionaware topology optimization of structured power/ground networks
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2005
"... This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the power grid chip area into rectangular subgrids or tiles. Treating the entire power grid to be composed of many tiles connect ..."
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Cited by 18 (5 self)
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This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the power grid chip area into rectangular subgrids or tiles. Treating the entire power grid to be composed of many tiles connected to each other enables the use of a hierarchical circuit analysis approach to identify the tiles containing the nodes having the greatest drops. Starting from an initial equal number of wires in each of the rectangular tiles, wires are added in the tiles using an iterative sensitivity based optimizer. A novel and efficient table lookup scheme is employed to provide gradient information to the optimizer. Experimental results on test circuits of practical chip sizes show that the proposed P/G network topology after optimization saves 16 % to 28 % of the chip wiring area over other commonly used topologies.
HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery
 IEEE Trans. ComputerAided Design
, 2005
"... Abstract—This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circ ..."
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Cited by 18 (3 self)
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Abstract—This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. The significant speed improvement, 700 times faster than Spice with less than 0.2 % error and 7 times faster than a stateoftheart solver, InductWise, is observed. To further reduce the toplevel hierarchy runtime, we develop a secondlevel model reduction algorithm and prove its passivity. Index Terms—Model order reduction, power distribution, power grid, signal integrity. I.
SPIE: Sparse Partial Inductance Extraction
 in DAC
, 1997
"... Extracting the inductance of complex interconnect topologies is a formidable task, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore, it is well known that simply discarding smallest terms to sparsify the inductance matrix can render the partial inducta ..."
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Cited by 18 (2 self)
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Extracting the inductance of complex interconnect topologies is a formidable task, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore, it is well known that simply discarding smallest terms to sparsify the inductance matrix can render the partial inductance matrix indefinite and result in an unstable circuit model. In this paper, we describe a methodology for incrementally generating a sparse partial inductance matrix based on using moments about s=0 to determine when a sufficient number of mutual inductances have been captured. The minimally required mutual inductances are extracted for a provably stable model. 1.0 Introduction Inductance extraction is difficult because mutual inductance depends on the current return path  which is unknown prior to extracting and simulating a circuit model. Rosa introduced the concept of partial inductances [1][5] to avoid this difficulty by assuming that each segment has a return current at infinity....
Efficient thermal simulation for runtime temperature tracking and management
 and management.In International Conference on Computer Design (ICCD
, 2005
"... As power density increases exponentially, runtime regulation of operating temperature by dynamic thermal management becomes imperative. This paper proposes a novel approach to realtime thermal estimation at chip level for efficient dynamic thermal management in lieu of the thermal sensors, which a ..."
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Cited by 14 (3 self)
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As power density increases exponentially, runtime regulation of operating temperature by dynamic thermal management becomes imperative. This paper proposes a novel approach to realtime thermal estimation at chip level for efficient dynamic thermal management in lieu of the thermal sensors, which are erroneous and having longer delays. Our new approach is based on the observation that the average power consumption of architecture level modules in microprocessors running typical workloads determines the trend of temperature variations. Such a feature can be exploited by applying fast moment matching technique in frequency domain. To obtain the transient temperature changes due to initial condition and constant power input pattern, numerically stable moment matching approach is carried out to speed up online temperature tracking with high accuracy and low overhead. The resulting fast thermal analysis algorithm has linear time complexity in runtime setting and leads to about two orders of magnitude speedup over traditional integrationbased transient analysis. The average maximum error under running typical benchmarks is only about 0.37 ◦ C as compared to other wellaccepted simulation tools. 1.
TETA: TransistorLevel Engine for Timing Analysis
 Proceedings of the Design Automation Conference
, 1998
"... TETA is an interconnectcentric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and large coupled RC(L) interconnect models. TETA applies a novel compaction for the transistor clusters and employs successive chord iterat ..."
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Cited by 13 (2 self)
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TETA is an interconnectcentric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and large coupled RC(L) interconnect models. TETA applies a novel compaction for the transistor clusters and employs successive chord iterations to solve the resulting nonlinear equations. These algorithms permit the use of simple SIMO (single input multioutput) Nport interconnect models since macromodel passivity is not required. The successive chord analysis also enables TETA to avoid the Nport matrix factorization during nonlinear iterations and allows the use of simple table lookup models for MOS devices. Complex gates and nonlinear capacitors can be handled without loss of generality. 1: Introduction For future CMOS technologies, a key feature of a transistor level timing engine will be the efficient handling of RLC interconnect. Coupling between signal paths transforms interconnecttree problems into Nport...
DTT: Direct Truncation of the Transfer Function  An Alternative to Moment Matching for Tree Structured Interconnect
 IEEE TRANS. COMPUTERAIDED DESIGN
, 2002
"... A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal. This method depends on finding a low frequency reducedorder transfer function by direct truncation of the exact transfer function at different nodes of an RLC tree. The m ..."
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Cited by 11 (0 self)
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A method is introduced to evaluate time domain signals within RLC trees with arbitrary accuracy in response to any input signal. This method depends on finding a low frequency reducedorder transfer function by direct truncation of the exact transfer function at different nodes of an RLC tree. The method is numerically accurate for any order of approximation, which permits approximations to be determined with a large number of poles appropriate for approximating RLC trees with underdamped responses. The method is computationally efficient with a complexity linearly proportional to the number of branches in an RLC tree. A common set of poles is determined that characterizes the responses at all of the nodes of an RLC tree which further enhances the computational efficiency. Stability is guaranteed by the DTT method for loworder approximations with less than five poles. Such loworder approximations are useful for evaluating monotone responses exhibited by RC circuits.
Optimization of Custom MOS Circuits by Transistor Sizing
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1996
"... Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to r ..."
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Cited by 11 (5 self)
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Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design highperformance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses