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Object-oriented programming languages confer many benefits, including abstraction, which lets the programmer hide the details of an object’s implementation from the object’s clients. Unfortunately, crossing abstraction boundaries often incurs a substantial run-time overhead in the form of frequent procedure calls. Thus, pervasive use of abstraction, while desirable from a design standpoint, may be impractical when it leads to inefficient programs. Aggressive compiler optimizations can reduce the overhead of abstraction. However, the long compilation times introduced by optimizing compilers delay the programming environment‘s responses to changes in the program. Furthermore, optimization also conflicts with source-level debugging. Thus, programmers are caught on the horns of two dilemmas: they have to choose between abstraction and efficiency, and between responsive programming environments and efficiency. This dissertation shows how to reconcile these seemingly contradictory goals by performing optimizations lazily. Four new techniques work together to achieve high performance and high responsiveness: • Type feedback achieves high performance by allowing the compiler to inline message sends based on information extracted from the runtime system. On average, programs run 1.5 times faster than the previous SELF system; compared to a commercial Smalltalk implementation, two medium-sized benchmarks run about three times faster. This level of performance is obtained with a compiler that is both simpler and faster than previous SELF compilers. • Adaptive optimization achieves high responsiveness without sacrificing performance by using a fast nonoptimizing compiler to generate initial code while automatically recompiling heavily used parts of the program with an optimizing compiler. On a previous-generation workstation like the SPARCstation-2, fewer than 200 pauses exceeded 200 ms during a 50-minute interaction, and 21 pauses exceeded one second. On a currentgeneration workstation, only 13 pauses exceed 400 ms. • Dynamic deoptimization shields the programmer from the complexity of debugging optimized code by transparently recreating non-optimized code as needed. No matter whether a program is optimized or not, it can always be stopped, inspected, and single-stepped. Compared to previous approaches, deoptimization allows more debugging while placing fewer restrictions on the optimizations that can be performed. • Polymorphic inline caching generates type-case sequences on-the-fly to speed up messages sent from the same call site to several different types of object. More significantly, they collect concrete type information for the optimizing compiler. With better performance yet good interactive behavior, these techniques make exploratory programming possible both for pure object-oriented languages and for application domains requiring higher ultimate performance, reconciling exploratory programming, ubiquitous abstraction, and high performance.

In this paper we discuss a selection of promising and interesting research areas in the design of protocols and systemsforwirelessindustrialcommunications.Wehaveselected topicsthathaveeitheremergedashottopicsintheindustrial communicationscommunityinthelastfewyears(likewireless sensornetworks),orwhichcouldbeworthwhileresearchtopicsin thenextfewyears(forexamplecooperativediversitytechniques for error control, cognitive radio/opportunistic spectrum access for mitigation of external interferences).

Abstract. Previous studies have shown that object-oriented programs have different execution characteristics than procedural programs, and that special object-oriented hardware can improve performance. The results of these studies may no longer hold because compiler optimizations can remove a large fraction of the differences. Our measurements show that SELF programs are more similar to C programs than are C++ programs, even though SELF is much more radically object-oriented than C++ and thus should differ much more from C. Furthermore, the benefit of tagged arithmetic instructions in the SPARC architecture (originally motivated by Smalltalk and Lisp implementations) appears to be small. Also, special hardware could hardly reduce message dispatch overhead since dispatch sequences are already very short. Two generic hardware features, instruction cache size and data cache write policy, have a much greater impact on performance. 1

The 802.11e working group has recently proposed the Hybrid Coordination Function (HCF) to provide service differentiation for supporting real-time transmissions over 802.11 Wireless Local Area Networks. The HCF is made of a contention-based channel access, known as Enhanced Distributed Coordination Access, and of a HCF Controlled Channel Access (HCCA), which requires a Hybrid Coordinator for bandwidth allocation to nodes hosting applications with QoS requirements. The 802.11e proposal includes a simple scheduler providing a Constant Bit Rate service, which is not well suited for bursty media flows. This paper proposes two feedback-based bandwidth allocation algorithms to be used within the HCCA, which have been referred to as Feedback Based Dynamic Scheduler (FBDS) and Proportional-Integral (PI)-FBDS. These algorithms have been designed with the objective of providing services with bounded delays. Given that the 802.11e standard allows queue lengths to be fed back, a control theoretic approach has been employed to design the FBDS, which exploits a simple proportional controller, and the PI-FBDS, which implements a proportional-integral controller. Proposed algorithms can be easily implemented since their computational complexities scale linearly with the number of traffic streams. Moreover, a Call Admission Control scheme has been proposed as an extension of the

Abstract. There has been considerable success in analytic modeling of the 802.11 MAC layer. These models are based on a number of fundamental assumptions. In this paper we attempt to verify these assumptions by taking careful measurements using an 802.11e testbed with commodity hardware. We show that the assumptions do not always hold but our measurements offer insight as to why the models may still produce good predictions. To our knowledge, this is the first in-detail attempt to compare 802.11 models and their assumptions with experimental measurements from an 802.11 testbed. The measurements collect also allow us to test if the basic MAC operation adhere to the 802.11 standards. 1

The IEEE 802.11e standard revises the Medium Access Control (MAC) layer of the former IEEE 802.11 standard for Quality-of-Service (QoS) provision in the Wireless Local Area Networks (WLANs). The Enhanced Distributed Channel Access (EDCA) function of 802.11e defines multiple Access Categories (AC) with AC-specific Contention Window (CW) sizes, Arbitration Interframe Space (AIFS) values, and Transmit Opportunity (TXOP) limits to support MAC-level QoS and prioritization. We propose an analytical model for the EDCA function which incorporates an accurate CW, AIFS, and TXOP differentiation at any traffic load. The proposed model is also shown to capture the effect of MAC layer buffer size on the performance. Analytical and simulation results are compared to demonstrate the accuracy of the proposed approach for varying traffic loads, EDCA parameters, and MAC layer buffer space. I.

The recently ratified IEEE 802.11e standard defines the Enhanced Distributed Channel Access (EDCA) function for Quality-of-Service (QoS) provisioning in the Wireless Local Area Networks (WLANs). The EDCA uses Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) and slotted Binary Exponential Backoff (BEB) mechanism. We present a simple mathematical analysis framework for the EDCA function. Our analysis considers the fact that the distributed random access systems exhibit cyclic behavior where each station successfully transmits a packet in a cycle. Our analysis shows that an AC-specific cycle time exists for the EDCA function. Validating the theoretical results via simulations, we show that the proposed analysis accurately captures EDCA saturation performance in terms of average throughput, medium access delay, and packet loss ratio. The cycle time analysis is a simple and insightful substitute for previously proposed more complex EDCA models. I.

In interleaved memories, interference between concurrently active vector streams results in memory bank conflicts and reduced bandwidth. In this paper, we present two schemes for reducing inter-vector interference. First, we propose a memory module partitioning technique in which disjoint access sets are created for each of the concurrent vectors. Various properties of the involved address mapping are presented. Then we present an interlaced data placement scheme, where the simultaneously accessed vectors are interlaced and stored to the memory. Performance of the two schemes are evaluated by trace driven simulation. It is observed that the schemes have significant merit in reducing the interference in interleaved memories and increasing the effective memory bandwidth. The schemes are applicable to memory systems for superscalar processors, vector supercomputers and parallel processors. Keywords: Address Distribution, Conflict-free access, Vector Interference, Memory Storage Patterns...

The report describes and discusses the requirements that control puts on networked embedded systems, in particular sensor networks and wireless mobile ad hoc networks. Two aspects of control are discussed. The first is control as an application, i.e., control over networks and the second is the use of control-based techniques for network resource management.