A single-chip, multi-mode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. Hence, the receiver operates at four different RF frequencies with two different baseband bandwidths. The presented chip, which consists of a low noise amplifier, downconversion mixers with on-chip LO I/Q-generation, channel selection filters, and programmable gain amplifiers, uses a direct conversion architecture. In spite of four receive bands, only four on-chip inductors are used in the single-ended low noise amplifier. The repeatable receiver IIP2 of over +42dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8dB in all GSM modes, and 3.5dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42mW and 50mW, respectively. The silicon area is 9.8mm 2 including the bonding pads. I.

This thesis describes the design and implementation of analog baseband circuits for low-power single-chip WCDMA direct-conversion receivers. The reference radio system throughout the thesis is UTRA/FDD. The analog baseband circuit consists of two similar channels, which contain analog channel-select filters, programmable-gain amplifiers, and circuits that remove DC offsets. The direct-conversion architecture is described and the UTRA/FDD system characteristics are summarized. The UTRA/FDD specifications define the performance requirement for the whole receiver. Therefore, the specifications for the analog baseband circuit are obtained from the receiver requirements through calculations performed by hand. When the power dissipation of an UTRA/FDD direct-conversion receiver is minimized, the design parameters of an all-pole analog channel-select filter and the following Nyquist rate analog-to-digital converter must be considered simultaneously. In this thesis, it is shown that minimum power consumption is achieved with a fifth-order lowpass filter and a 15.36-MS/s Nyquist rate converter that has a 7- or 8-bit resolution. A fifth-order Chebyshev prototype with a passband ripple of 0.01dB and a –3-dB frequency of 1.92-MHz is adopted in this thesis. The