Results 1  10
of
10
A Simple Linear Time Algorithm for Proper Box Rectangular Drawing of Plane Graphs
 Journal of Algorithms
, 2000
"... In this paper we introduce a new drawing style of a plane graph G, called proper box rectangular (PBR ) drawing. It is defined to be a drawing of G such that every vertex is drawn as a rectangle, called a box, each edge is drawn as either a horizontal or a vertical line segment, and each face is dra ..."
Abstract

Cited by 6 (0 self)
 Add to MetaCart
In this paper we introduce a new drawing style of a plane graph G, called proper box rectangular (PBR ) drawing. It is defined to be a drawing of G such that every vertex is drawn as a rectangle, called a box, each edge is drawn as either a horizontal or a vertical line segment, and each face is drawn as a rectangle. We establish necessary and sufficient conditions for G to have a PBR drawing. We also give a simple linear time algorithm for finding such drawings. The PBR drawing is closely related to the box rectangular (BR ) drawing defined by Rahman, Nakano and Nishizeki [17]. Our method can be adapted to provide a new simpler algorithm for solving the BR drawing problem. 1 Introduction The problem of "nicely" drawing a graph G has received increasing attention [5]. Typically, we want to draw the edges and the vertices of G on the plane so that certain aesthetic quality conditions and/or optimization measures are met. Such drawings are very useful in visualizing planar graphs and fi...
S.: Euclidean Representation of 3D electronic institutions: Automatic Generation
 In: Proceedings of the 8th International Working Conference on Advanced Visual Interfaces (AVI
, 2006
"... In this paper we present the 3D Electronic Institutions metaphor and show how it can be used for the specification of highly secure Virtual Worlds and how 3D Virtual Worlds can be automatically generated from this specification. To achieve the generation task we propose an algorithm for automatic tr ..."
Abstract

Cited by 5 (3 self)
 Add to MetaCart
In this paper we present the 3D Electronic Institutions metaphor and show how it can be used for the specification of highly secure Virtual Worlds and how 3D Virtual Worlds can be automatically generated from this specification. To achieve the generation task we propose an algorithm for automatic transformation of the Performative Structure graph into a 3D Virtual World, using the rectangular dualization technique. The nodes of the initial graph are transformed into rooms, the connecting arcs between nodes determine which rooms have to be placed next to each other and define the positions of the doors connecting those rooms. The proposed algorithm is sufficiently general to be used for transforming any planar graph into a 3D Virtual World.
From Graphs to Euclidean Virtual Worlds: Visualization of 3D Electronic Institutions
"... In this paper we propose an algorithm for automatic transformation of a graph into a 3D Virtual World and its Euclidean map, using the rectangular dualization technique. The nodes of the initial graph are transformed into rooms, the connecting arcs between nodes determine which rooms have to be plac ..."
Abstract

Cited by 4 (4 self)
 Add to MetaCart
In this paper we propose an algorithm for automatic transformation of a graph into a 3D Virtual World and its Euclidean map, using the rectangular dualization technique. The nodes of the initial graph are transformed into rooms, the connecting arcs between nodes determine which rooms have to be placed next to each other and define the positions of the doors connecting those rooms. The proposed algorithm is general enough to be used for automatic generation of 3D Virtual Worlds representation of any planar graph, however, our research is particulary focused on the automatic generation of 3D Electronic Institutions from the Performative Structure graph.
Efficient Algorithms for Drawing Planar Graphs
, 1999
"... x 1 Introduction 1 1.1 Historical Background . . .............................. 4 1.2 Drawing Styles . ................................... 4 1.2.1 Polyline drawings .............................. 5 1.2.2 Planar drawings ............................... 5 1.2.3 Straight line drawings ................. ..."
Abstract

Cited by 1 (0 self)
 Add to MetaCart
x 1 Introduction 1 1.1 Historical Background . . .............................. 4 1.2 Drawing Styles . ................................... 4 1.2.1 Polyline drawings .............................. 5 1.2.2 Planar drawings ............................... 5 1.2.3 Straight line drawings ............................ 6 1.2.4 Orthogonal drawings . . ........................... 7 1.2.5 Grid drawings ................................ 8 1.3 Properties of Drawings ................................ 9 1.4 Scope of this Thesis .................................. 10 1.4.1 Rectangular drawings . . . ......................... 11 1.4.2 Orthogonal drawings . . ........................... 12 1.4.3 Boxrectangular drawings ........................... 14 1.4.4 Convex drawings . . ............................. 16 1.5 Summary ....................................... 16 2 Preliminaries 20 2.1 Basic Terminology .................................. 20 2.1.1 Graphs and Multigraphs ........................... 20 i CO...
Complexity of 3D Floorplans by Analysis of Graph Cuboidal Dual Hardness
"... Interconnect dominated electronic design stimulates a demand for developing circuits on the third dimension, leading to 3D integration. Recent advances in chip fabrication technology enable 3D circuit manufacturing. However, there is still a possible barrier of design complexity in exploiting 3D ..."
Abstract
 Add to MetaCart
Interconnect dominated electronic design stimulates a demand for developing circuits on the third dimension, leading to 3D integration. Recent advances in chip fabrication technology enable 3D circuit manufacturing. However, there is still a possible barrier of design complexity in exploiting 3D technologies. This article discusses the impact of migrating from 2D to 3D on the difficulty of floorplanning and placement. By looking at a basic formulation of the graph cuboidal dual problem, we show that the 3D cases and the 3layer 2.5D cases are fundamentally more difficult than the 2D cases in terms of computational complexity. By comparison among these cases, the intrinsic complexity in 3D floorplan structures is revealed in the hardtodecide relations between topological connections and geometrical contacts. The results show possible challenges in the future for physical design and CAD of 3D integrated circuits.
On the Complexity of Graph Cuboidal Dual Problems for 3D Floorplanning of Integrated Circuit Design
"... This paper discusses the impact of migrating from 2D to 3D on floorplanning and placement. By looking at a basic formulation of graph cuboidal dual problem, we show that the 3D case and the 3layer 2.5D case are fundamentally more difficult than the 2D case in terms of computational complexity. ..."
Abstract
 Add to MetaCart
This paper discusses the impact of migrating from 2D to 3D on floorplanning and placement. By looking at a basic formulation of graph cuboidal dual problem, we show that the 3D case and the 3layer 2.5D case are fundamentally more difficult than the 2D case in terms of computational complexity. By comparison among these cases, the intrinsic complexity in 3D floorplan structures is revealed in the harddeciding relations between topological connections and geometrical contacts. The results show future challenges for physical design and CAD of 3D integrated circuits. Categories and Subject Descriptors J.6 [Computer Applications]: Computeraided design General terms – Algorithms, theory
An Extended Representation of Qsequence for Optimizing ChannelAdjacency and RoutingCost
"... Abstract — This paper proposes a topological representation for general floorplan, called the Hsequence, which can check channeladjacency and boundaryadjacency in a constant time. Moreover, we define Routingcost for the placement to measure its routing difficulty. Experimental results indicate t ..."
Abstract
 Add to MetaCart
Abstract — This paper proposes a topological representation for general floorplan, called the Hsequence, which can check channeladjacency and boundaryadjacency in a constant time. Moreover, we define Routingcost for the placement to measure its routing difficulty. Experimental results indicate that Hsequence based placement algorithm can optimize routingcost effectively in a short time. A. Background I.
Coding Floorplans with Fewer Bits
, 2006
"... A naive coding of floorplans needs 2m bits for each floorplan. In this paper we give a new simple coding of floorplans, which needs only 5m/3 bits for each floorplan. ..."
Abstract
 Add to MetaCart
A naive coding of floorplans needs 2m bits for each floorplan. In this paper we give a new simple coding of floorplans, which needs only 5m/3 bits for each floorplan.