Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs o#er the best power e#ciency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-o# between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power. The use of multiple supply voltages presents some unique physical and electrical challenges. Level shifters need to be introduced between the various voltage regions. Several level shifter implementations will be shown. The physical layout needs to be designed to ensure the e#cient delivery of the correct voltage to various voltage regions. More flexibility can be gained by using appropriate level shifters. We will discuss optimization techniques such as clock skew scheduling which can be e#ectively used to push performance in a power neutral way.

The design of power distribution networks in high performance integrated circuits has become significantly more challenging with recent advances in process technology. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of the on-chip power supply has become a primary concern in integrated circuit design. The existing work on power distribution noise scaling is reviewed and extended to include the scaling of the inductance of the on-chip global power distribution networks in high performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S> 1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S 2 in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling in the global power grid mitigates unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will therefore become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise levels.

Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, circuit design and micro-architectural changes are required. Consequently, to focus the optimization efforts in the right direction, the models proposed and studies performed in this work are a first step for understanding the relative importance of leakage and dynamic energy in future technologies. Further, we analyze the effectiveness of two energy reduction mechanisms that employ voltage scaling, namely, supply and threshold voltage selection. We consider the impact of imminent technology changes and packaging improvements while showing that neglecting the impact of temperature may lead to underestimate the power savings by up to 19.5%.

Thermal management is becoming increasingly important in circuit designs with high power density. Circuits that overheat beyond specified operating conditions may suffer timing failures, or become damaged for various reasons, including thermal runaway. Traditional power management in synchronous systems often involves transitions to different system states or modes, typically involving changes in clock frequencies or voltage levels. However, the self-timed nature of asynchronous circuits allows delays to vary continuously during operation, enabling stall-free performance-throttling. We present a novel application of a thermally sensitive circuit to automatically regulate the performance and power consumption of asynchronous circuits, with minimal implementation overhead. 1

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Thermal management is becoming increasingly important in circuit designs with high power density. Circuits that overheat beyond specified operating conditions may suffer timing failures, or become damaged for various reasons, including thermal runaway. We present a novel application of a thermally sensitive circuit to automatically regulate the performance and power consumption of asynchronous circuits, with minimal implementation overhead, and free of interruption of operation. 1

Increasing design and manufacturing costs are prompting a shift in electronic design from hardwired application-specific integrated circuits (ASICs) to the use of software on programmable platforms. In order to minimize the power and performance over-head of such platforms, domain or application-specific processors have been used. The development of such processors requires not only traditional electronic design automation tools but also processor-specific software tools such as compilers and in-struction set simulators. In early development stages when multiple processor design points are explored, it is necessary to have the software tools synthesized from high level processor descriptions. This dissertation presents an approach that aims to automate the synthesis of these software tools. The foundation of the approach is a novel concurrency model, the operation state machine (OSM). The OSM model views a processor in two interacting levels: the operation level where instruction be-havior is represented and the hardware level where resources required for instruction execution are managed. Through proper abstraction, the model significantly sim-plifies the specification of concurrency and control semantics without compromising flexibility. This dissertation then presents the MESCAL Architecture Description Language (MADL) which is designed using the OSM model. It describes the major design considerations of MADL and the synthesis of software tools including cycle-iii accurate simulators, instruction set simulators, disassemblers, and binary decoders from MADL-based processor models. It further goes on to show how this description can be used to extract reservation tables for use in instruction schedulers in compil-ers. Experimental results show that the MADL-based approach is very effective in supporting these software tools and the synthesized cycle-accurate simulators have competitive simulation speeds compared to their hand-coded counterparts.

Abstract- Global signaling is becoming more and more challenging as technology scales down toward the deep submicron. We propose a new bus encoding technique, transition skew coding, that targets many of the global interconnects challenges such as crosstalk, peak energy and current, switching and leakage power, repeaters area, wiring area, signal integrity and noise. Simulations are done on different bus lengths using a 90nm library. Repeaters sizing and spacing are optimized, and the proposed encoded bus is compared against a standard bus and a bus with shields inserted between every two wires. The encoding and decoding latencies are also analyzed. Simulations show that transition skew coding is efficient in terms of energy