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Boolean analysis of MOS circuits
 IEEE Transactions on Computeraided Design
, 1987
"... The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically ..."
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Cited by 63 (14 self)
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The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network state. This analysis supports the same class of networks as the switchlevel simulator MOSSIM II and provides the same functionality, including the handling of bidirectional e ects and indeterminate (X) logic values. In the worst case, the analysis of an n node network can yield a set of formulas containing a total of O(n 3) operations. However, all but a limited set of dense, passtransistor networks give formulas with O(n) total operations. The analysis can serve as the basis of e cient programs for a variety oflogic design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test generation, and symbolic veri cation.
COSMOS: A compiled simulator for MOS circuits
 PROCEEDINGS OF THE 24TH DESIGN AUTOMATION CONFERENCE
, 1987
"... The cosmos simulator provides fast and accurate switchlevel modeling of mos digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer anamos, captures all aspects o ..."
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Cited by 52 (0 self)
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The cosmos simulator provides fast and accurate switchlevel modeling of mos digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer anamos, captures all aspects of switchlevel networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The lgcc program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator mossim ii.
Error diagnosis for transistorlevel veri  cation
 Tech. Rep. Computer Science, RC 19219 (#83668), IBM Research Division, T. J. Watson Research Center, Yorktown Heights, NY
, 1993
"... This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional speci cation. The method e ciently propagates mismatched patterns from erroneous outputs backward into the network and calculates circuit regions which most likely con ..."
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Cited by 27 (3 self)
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This paper describes a diagnosis technique for locating design errors in circuit implementations which do not match their functional speci cation. The method e ciently propagates mismatched patterns from erroneous outputs backward into the network and calculates circuit regions which most likely contain the error(s). In contrast to previous approaches, the described technique does not depend on a xed set of error models. Therefore, it is more general and especially suitable for transistorlevel circuits, which have a broader variety of possible design errors than gatelevel implementations. Furthermore, the proposed method is also applicable for incomplete sets of mismatched patterns and hence can be used not only as a debugging aid for formal veri cation techniques but also for simulationbased approaches. Experiments with industrial CMOS circuits show that for most design errors the identi ed problem region is less than 3 % of the overall circuit. 1
Verity  a Formal Verification Program for Custom CMOS Circuits
 IBM JOURNAL OF RESEARCH AND DEVELOPMENT
, 1994
"... In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correc ..."
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Cited by 19 (5 self)
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In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a highlevel design specification and a MOS transistorlevel implementation. Verity
Algorithmic Aspects of Symbolic Switch Network Analysis
 IEEE Trans. CAD/IC
, 1987
"... A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean eq ..."
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Cited by 16 (5 self)
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A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean equations. For the class of networks that arise when analyzing digital metaloxide semiconductor (MOS) circuits, a simple pivot selection rule guarantees that most s switch networks encountered in practice can be solved with O(s) operations. When represented by a directed acyclic graph, the set of Boolean formulas generated by the analysis has total size bounded by the number of operations required by the Gaussian elimination. This paper presents the mathematical basis for systems of Boolean equations, their solution by Gaussian elimination, and data structures and algorithms for representing and manipulating Boolean formulas.
Symbolic Verification of MOS Circuits
, 1985
"... The program MOSSYM simulates the behavior of a MOS circuit represented as a switchlevel network symbolically. That is, during simulator operation the user can set an input to either 0, 1, or a Boolean variable. The simulator then computes the behavior of the circuit as a function of the past and pr ..."
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Cited by 13 (6 self)
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The program MOSSYM simulates the behavior of a MOS circuit represented as a switchlevel network symbolically. That is, during simulator operation the user can set an input to either 0, 1, or a Boolean variable. The simulator then computes the behavior of the circuit as a function of the past and present input variables. By using heuristically efficient Boolean function manipulation algorithms, the verification of a circuit by symbolic simulation can proceed much more quickly than by exhaustive logic simulation. In this paper we present our concept of symbolic simulation, derive an algorithm for switchlevel symbolic simulation, and present experimental measurements from MOSSYM.