This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC---a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language co...

Many computationally-intensive tasks spend nearly all of their execution time within a small fraction of the executable code. A new hardware/software system, called PRISM, is presented which improves the performance of many of these computationally intensive tasks by utilizing information extracted at compile-time to synthesize new operations which augment the functionality of a core processor. By integrating adaptation into a general-purpose computer, one can not only reap the performance benefits of applicationspecific processors, but also retain the general-purpose nature by accommodating a wide variety of tasks. Newly synthesized operations are targeted to RAM-based logic devices which provide a mechanism for fast processor reconfiguration. A proof-of-concept system called PRISM-I, consisting of a specialized C configuration compiler and a reconfigurable hardware platform is presented. Compilation and performance results are provided which confirm the concept viability, and demonstrate significant speed-up over conventional general-purpose architectures. Keywords: Adaptive Architectures, Reconfigurable Instruction Sets, Performance Improvements, General-Purpose Computers, Logic Synthesis I

A Dynamic Instruction Set Computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space. 1 Introduction Developing customized stored-program processors is a convenient design technique that combines the enhanced performance of application-specific circuits with the flexibility of general-purpose programmable processors. Application-specific instruction sets, customized I/O and optimized control can substantially improve the performance of even the simplest programmable pro...

A Dynamic Instruction Set Computer (DISC) has been developed to support demand-driven instruction set modification. Using partial reconfiguration, DISC pages instruction modules in and out of an FPGA as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space. An image processing application was developed on DISC to demonstrate the advantages of paging application-specific instruction modules. Keywords: FPGA processor, run-time reconfiguration, relocatable hardware, application-specific processor 1 INTRODUCTION For many digital systems, general purpose processors do not provide sufficient processing power to operate acceptably in real-time environments. Specialized computing resources, such as digital signal p...

This dissertation presents the thesis that good and usable instruction sets can be automatically derived for a specified data path and benchmark set. This is achieved by a multistep process: generating execution traces for the benchmark programs, sampling these traces to form a large set of small code segments, optimally recompiling these segments using exhaustive search, and finding the cover of the new instructions generated that optimizes the performance metric. The complete process is illustrated by generating an instruction set for a processor optimized for executing compiled Prolog programs. The generated instruction set is compared with the hand-designed VLSI-BAM instruction set. The automatically designed instruction set is smaller and has only a few percent less performance on th...

Many people deserve thanks for helping me navigate through my PhD. First and foremost, I must thank my wife, Stephanie, for her loving support without which I certainly would not have succeeded. She is a wonderful companion, and I feel like the luckiest man on the planet to be married to her. I thank her for her patience through my many long work days, and for helping me stay sane through my many deadlines. My parents, Art and Nancy, were also extremely supportive throughout my six years in graduate school. I greatly appreciated their loving phone calls, emails, and visits. They have always been there for me. I also must thank, my brother, Ryan, my grandmother, Barbara, as well as Stephanie’s family. Their encouragement and loving support certainly helped me through my PhD. My advisor, E Christopher Lewis, is chiefly responsible for my academic and professional development. I have benefitted profusely from his guidance and support. I learned from E what it means to deeply understand a research problem, and to always consider the broader impact of my research. E is also an incredible teacher, breaking the most complicated concepts down into simple manageable pieces. I will try to emulate these skills

The Reconfigurable and Adaptive Computing Environment, or RACE, is a reconfigurable computer that has been developed in the Design Automation Laboratory at the University of Cincinnati. RACE was developed to facilitate any type of reconfigurable computing. Reconfigurable computing can be thought of as having the ability to repeatedly perform applications on a reconfigurable hardware system. Such reconfigurable hardware has been made possible by the advent of FPGAs, or Field-Programmable Gate Arrays. The RACE system has five Xilinx XC4013 FPGAs, one of which acts as a controller, which provide approximately 52,000 logic gates for computing. Furthermore, each FPGA has 128KB of local data memory and 64KB of local configuration memory, which is used to store FPGA configurations. RACE was designed to make reconfigurable computing easy to use so a library of software functions have been developed to control the reconfigurable hardware without detailed hardware knowledge of RACE. Likewise, im...

PRISM, a computer architecture consisting of a generalpurpose core processor and a reconfigurable FPGA platform, was designed to bridge the gap between general-purpose and specialized computers. PRISM-I, introduced a new concept wherein a custom architecture, utilizing the FPGAs, is dynamically and automatically created to execute a specific C program more efficiently. Speedup is achieved by executing frequently executed functions of the program on the custom-synthesized hardware while the remainder of the program executes on the core processor. PRISM-I, however, being a proof-of-concept system, suffers from several limitations, principal among them being that the evaluation time of a function is restricted to a single bus-cycle, loops with variable iteration counts are not allowed in the function, and control constructs, i.e. "if-thenelse ", are not executed efficiently. This paper introduces a significant conceptual advancement, PRISM-II, that synthesizes asynchronous, adaptive architectures for C programs and addresses the above limitations of PRISM-I in a general manner. PRISM-II introduces a novel execution model and a framework for translating a C function into an FPGA-based custom architecture. 1.

Dynamic Instruction Stream Editing (DISE) is a cooperative software-hardware scheme for efficiently adding meta-features---e.g., safety/security checking, profiling, and dynamic code decompression---to an application. DISE implements meta-features by providing a programmable processor decoder that macro-expands certain instructions into parameterized instruction sequences. The technique is similar in spirit to programmable microcode and exploits the macro-expansion-style decoding technology already present in many of today's processors. DISE is a