A 64 x 64-pixel analog image filtering processor has been developed. The chip employs the scanning lineparallel processing architecture in order to realize a very fast execution of image filtering operation. In addition, any typical filtering kernels are programmable in this architecture. The line parallel processing is carried out for the pixels in a single row or the pixels in a single column at one time. The essence of the processing is that in the row parallel processing all necessary matrix multiplications in the column direction are carried out simultaneously, and that the rest of the matrix multiplication is completed in the column parallel processing that follows. The entire image filtering operation is completed by just scanning the line processing in both vertical and horizontal directions. As a result, the number of cycles required for the total operation is only in the order of M + N for an M x N-pixel image. A prototype chip of 64 x 64-pixel array was fabricated in a 0.6-µm double-polysilicon triple-metal CMOS technology, and the proposed concept has been experimentally demonstrated. 1.