The continued drive toward technology scaling in VLSI design has provided greater integration levels in silicon chips. Thanks to the reduction in minimum feature size and the corresponding decrease in power supply voltage, digital circuits have bene-fited from savings in area and power consumption. This approach presents a number of challenges in Complementary Metal-Oxide Semiconductor (CMOS) analog circuit design. As the gate oxide of transistors becomes thinner and power consumption increases, a lower supply voltage must be used, even though it results in performance degradation of analog circuits. This must be done in order to avoid silicon punch-through. In applications requiring low power consumption and moderate conversion speed, one of the most frequently used analog-to-digital converter (ADC) architec-tures is the successive approximation. As data converters are mixed-signal circuits, containing both analog and digital circuits, they suffer from the same problems just described. This thesis presents the design of a low-voltage successive approximation ADC based on a Switched Opamp comparator. The proposed comparator archi-

Abstract –A techrdqrre for pulsecode modulation (PCM) encoding ac-cording to the 15-segment approximation to the P-255 krw is deseribed. The technique makes possible the realization of a one-channel encoder together with the associated sample/hold function as a single NMOS integrated circuit. The requirements imposed on the individual com-ponents for satisfactory system performance are investigated, and it is shown that a performance can be achieved which is comparable with that required in toll qualit y PCM telephone transmission. Experimental results from a partiatly integrated prototype are presented.