This paper introduces Bitwise, a compiler that minimizes the bitwidth --- the number of bits used to representeach operand --- for both integers and pointers in a program. By propagating static information both forward and backward in the program dataflowgraph,Bitwise frees the programmer from declaring bitwidth invariants in cases where the compiler can determine bitwidths automatically. We find a rich opportunity for bitwidth reduction in modern multimedia and streaming application workloads. For new architectures that support sub-word quantities, we expect that our bitwidth reductions will savepower and increase processor performance. This paper

interpreters, run-time environments; F.3.2 [Logics

Although the C-based interpreter of Python is reasonably fast, implementations on the CLI or the JVM platforms offers some advantages in terms of robustness and interoperability. Unfortunately, because the CLI and JVM are primarily designed to execute statically typed, object-oriented languages, most dynamic language implementations cannot use the native bytecodes for common operations like method calls and exception handling; as a result, they are not able to take full advantage of the power offered by the CLI and JVM. We describe a different approach that attempts to preserve the flexibility of Python, while still allowing for efficient execution. This is achieved by limiting the use of the more dynamic features of Python to an initial, bootstrapping phase. This phase is used to construct a final RPython (Restricted Python) program that is actually executed. RPython is a proper subset of Python, is statically typed, and does not allow dynamic modification of class or method definitions; however, it can still take advantage of Python features such as mixins and first-class methods and classes. This paper presents an overview of RPython, including its design and its translation to both CLI and JVM bytecode. We show how the bootstrapping phase can be used to implement advanced features, like extensible classes and generative programming. We also discuss what work remains before RPython is truly ready for general use, and compare the performance of RPython with that of other approaches.

In real-time and embedded systems, it is often necessary to place conservative upper bounds on the memory required by a program or subprogram. This can be difficult and error-prone process. In this thesis, I have designed and implemented two (related) compile-time analyses to addresses this problem. The first analysis computes a symbolic upper bound on the maximum number of allocations of each object, showing undetermined facts about the program as symbols. The second analysis determines objects in the program that may be allocated statically, without changing the semantics of the program. The symbolic expression is then simplified by removing factors for statically allocated objects. The overall result is a simplified procedure for computing conservative upper bounds on memory. Results on a number of benchmarks are provided.

We present an improved slicing algorithm for Java. The best algorithm known so far, first presented in [11], is not always precise if nested objects are used as actual parameters. The new algorithm presented in this paper always generates correct and precise slices, but is more expensive in general.

This paper introduces an automatic debugging framework that relies on model–based reasoning techniques to locate faults in programs. In particular, model–based diagnosis, together with an abstract interpretation based conflict detection mechanism is used to derive diagnoses, which correspond to possible faults in programs. Design information and partial specifications are applied to guide a model revision process, which allows for automatic detection and correction of structural faults.

The static single assignment (SSA) form [CFR + 91] is now an established compiler intermediate representation.Sun’s HotSpot [Sun99] and Microsoft’s Marmot

We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an AFPGA. The resulting circuits are inherently pipelined, and can be physically mapped onto our AFPGA with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the FPGA. Categories and Subject Descriptors

Static Single Assignment Form is a common intermediate representation for optimizing compilers but several of its features are difficult to implement in a traditional imperative interpreter. An interpreter for Static Single Assignment would enable mixed-mode (interpreting and compiling) virtual machines to be developed around program representations in Static Single Assignment Form. We propose an extension to Static Single Assignment Form, Interpretable Static Single Assignment (ISSA). Each of Interpretable Static Single Assignment's instructions, including the phi instruction, has self-contained operational semantics. In addition, we describe a prototype interpreter of Interpretable Static Single Assignment and report on its performance.

Static single information form is a natural extension of the well-known static single assignment form. It is a program intermediate representation used in optimising compilers for imperative programming languages. In this paper we show how a program expressed in static single information form can be transformed into an equivalent program in functional notation. We also examine the implications of this transformation.