With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package’s capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies. This paper describes HotSpot, an accurate yet fast model based on an equivalent circuit of thermal resistances and capacitances that correspond to microarchitecture blocks and essential aspects of the thermal package. Validation was performed using finiteelement simulation. The paper also introduces several effective methods for dynamic thermal management (DTM): “temperaturetracking” frequency scaling, localized toggling, and migrating computation to spare hardware units. Modeling temperature at the microarchitecture level also shows that power metrics are poor predictors of temperature, and that sensor imprecision has a substantial impact on the performance of DTM. 1.

This paper proposes the use of formal feedback control theory as a way to implement adaptive techniques in the processor architecture. Dynamic thermal management (DTM) is used as a test vehicle, and variations of a PID controller (Proportional-Integral-Differential) are developed and tested for adaptive control of fetch "toggling." To accurately test the DTM mechanism being proposed, this paper also develops a thermal model based on lumped thermal resistances and thermal capacitances. This model is computationally efficient and tracks temperature at the granularity of individual functional blocks within the processor. Because localized heating occurs much faster than chip-wide heating, some parts of the processor are more likely to be "hot spots" than others.

In this paper, we study temperature-constrained hard realtime systems, where real-time guarantees must be met without exceeding safe temperature levels within the processor. Dynamic speed scaling is one of the major techniques to manage power so as to maintain safe temperature levels. As example, we adopt a simple reactive speed control technique in our work. We design a methodology to perform delay analysis for general task arrivals under reactive speed control with First-In-First-Out (FIFO) scheduling and Static-Priority (SP) scheduling. As a special case, we obtain a close-form delay formula for the leakybucket task arrival model. Our data show how simple reactive speed control can decrease the delay of tasks compared with any constant-speed scheme. 1

The most recent, and arguably one of the most difficult obstacles to the exponential growth in transistor density predicted by Moore’s Law is that of removing the large amount of heat generated within the tiny area of a microprocessor. The exponential increase in power density and its direct relation to on-chip temperature have, in recent processors, led to very high cooling costs. Since temperature also has an exponential effect on lifetime reliability and leakage power, it has become a first-class design constraint in microprocessor development akin to performance. This dissertation describes work to address the temperature challenge from the perspective of the architecture of the microprocessor. It proposes both the infrastructure to model the problem and several mechanisms that form part of the solution. This research describes HotSpot, an efficient and extensible microarchitectural thermal modeling tool that is used to guide the design and evaluation of various thermal management techniques. It presents several Dynamic Thermal Management (DTM) schemes that distribute heat both over time and space by controlling the level of computational activity. Processor temperature is not only a function of the power density but also the placement and adjacency of hot and cold functional blocks, determined by the floorplan of the microprocessor. Hence, this dissertation also explores various thermally mitigating placement choices