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When expanding digital signal processing of mobile communications terminals toward the antenna while making the terminal more wideband in order to be able to cope with different mobile communications standards in a software-radio-based terminal, the designer is faced with strong requirements such as bandwidth and dynamic range. Many publications claim that only reconfigurable hardware such as FPGAs can simultaneously cope with such diversity and requirements. Starting with considerations of the receiver architecture, we describe key functionalities of the digital front-end and highlight how signal characteristics of mobile communications signals and commonalities among different signal processing operations can be exploited to great advantage, eventually enabling implementations on an ASIC that, although not reconfigurable, would empower the software radio concept.

Software radio terminals must be able to process different communications standards which are generally based on different master clock rates and thus employ different bit/chip-rates. A straightforward solution to cope with this diversity of master clock rates in one terminal is to employ dedicated master clocks for each standard of operation. Being too costly in most cases, this kind of solution moreover limits the applicability of a once realized and thus fixed terminal. The smart solution to this problem is to run the terminal on a fixed clock rate, and to perform digital sample rate conversion that can be controlled by software and thus, empowers the software radio concept.

Frequency sampling filters (FSF) are of interest to the designers of multirate filter banks due to their intrinsic loworder, complexity, and linear phase behavior. Fast FSFs residing in smaller packages will be required to support future high-bandwidth, mobile image and signal processing applications. Since FSF designs rely on the exact annihilation of selected poles-zeros, a new facilitating technology is required which is fast, compact, and numerically exact. Exact FSF pole-zero annihilation is guaranteed by implementing polynomial filters over an integer ring in the residue arithmetic system (RNS). The design methodology is evaluated as an ASIC. Based on an FPGA technology, at least an 86% complexity reduction can be achieved with even greater advantages gained as a custom VLSI. An RNS-based FSF implementation of an eight channel cochlea filter bank is presented which demonstrates both the performance and packaging advantages of the new FSF paradigm. . 1. INTRODUCTION A classical f...

Recent efforts in the design of wireless RF transceivers focus on high integration and multi-standard operation. Higher integration can be obtained by using receiver architectures, such as wide-band IF with double conversion (WIF), that perform channel select filtering on-chip at baseband. Performing this baseband channel select filtering in the digital domain allows for the programmability necessary to adapt to the different channel bandwidths, sampling rates, and CNR requirements of multiple communication standards. At the back of a wide-dynamic range sigma-delta modulator, a decimation filter can select a desired channel in the presence of both strong adjacent channel interferers and quantization noise from the digitization process. A low-power decimation filter that performs channel select filtering for the GSM (European cellular) and DECT (European cordless) standards is presented. Automatic gain control is used within the filter to reduce the dynamic range and power consumption. Since the two standards have different blocking profiles and CNR i

A power efficient multi-rate multi-stage Comb decimation filter for mono-bit and multi-bit A A/D converters is presented. Polyphase decomposition in all stages, with high decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb filter. Several implementations indicate that proper choice of the first stage decimation factor can considerably improve power consumption, area and maximum sampling frequency. In multibit .A A/Ds, this optimum first stage decimation factor is function of the input wordlength.

In mobile communications systems complexity and efficiency are issues of paramount importance. Therefore when implementing integer factor sample-rate conversion, comb-filters - especially cascaded-integratorcomb (CIC) filters - are a good choice of realizing linearphase filters with low complexity. However, neither the direct implementation of comb-filters as transversal filters nor their implementation as CIC-filters are minimal realizations. Since both, decimators and interpolators are time-variant systems the minimal realization is certainly time-variant either. Based on an equivalent blockprocessing structure of the original system such timevariant realizations can be found. In the case of combfilters this results in halving the number of registers at the cost of multipliers though.

This paper presents an architecture for multi-mode terminals, strictly speaking multi-mode receivers, exploiting IF sampling with Sigma-Delta ADCs. It is shown that Sigma-Delta ADCs are not only an efficient means of digitizing signals but are a nearly perfect fit to the task of analog-to-digital conversion in multi-mode terminals. For further processing the digitized signal, i.e. channel filtering for FDMA systems as well as decorrelation for spread-spectrum systems, a common hardware is presented.

This contribution deals with a fully digital multirate radio receiver with IF sampling. Timing correction and sample rate conversion are performed by a polynomial interpolator. By performing interpolation prior to matched filtering a significant reduction in complexity may be achieved. Low degradations are attainable when the receiver design parameters are carefully chosen. If this is not possible, digital anti-aliasing filters are required. We investigate the computational complexity and BER performance when efficient cascaded integrator-comb (CIC) filters are employed to perform anti-aliasing. We show how some of the side-effects of CIC filters may be overcome and how CIC parameters may be selected to provide acceptable BER degradations for all symbol rates.

Multirate signal processing is an enabling technology that brings DSP techniques to applications requiring low-cost and high sample rates. Field programmable gate arrays (FPGAs) provide system-level hardware solutions for signal processing architects demanding both high-performance and flexibility. This workshop provides an introduction to the fundamental theory of multirate filter techniques and provides simple descriptions of polyphase decimators and interpolators. Wavelet theory has development roots in both mathematics and signal processing communities. In this workshop we will explain wavelet theory from both a signal expansion and filter bank viewpoint. Classes of signal processing problems that can benefit from wavelet techniques will be presented with simple examples. Implementation of mulitrate filters and wavelet structures with FPGAs will be explained for real time applications.