Abstract—A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6- m CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices. Index Terms — Amplifier noise, induced gate noise, low noise amplifier, microwave amplifier, MOSFET amplifier, noise figure, random noise, semiconductor device noise. I.

Abstract—A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and shortchannel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/ � noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed. Index Terms—Design methodology, jitter, noise measurement, oscillator noise, oscillator stability, phase jitter, phase-locked loops, phase noise, ring oscillators, voltage-controlled oscillators. I.

Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs--AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...

Abstract—This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance PP. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the parameters are established and compared to measurements made on a 0.25- m CMOS process. The parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the-parameter measurement. Index Terms—Modeling, MOS devices, MOSFET’s, RF CMOS IC, semiconductor device modeling, semiconductor device noise,

Abstract not found

analog-to-digital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18- m 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mmP and dissipates 98 mW. Index Terms—Analog integrated circuits, capacitor mismatch, comparator sharing, discrete-time common-mode voltage regulation, early comparison, low power, low voltage, nested CMOS gain boosting, opamp sharing, passive capacitor error-averaging, pipeline analog-to-digital converter, pseudo-differential, subsampling. I.

A 900 MHz low-noise amplifier (LNA) utilizing three monolithic transformers to implement on-chip tuning networks and requiring no external components has been integrated in 2.88 mm 2 in a standard digital 0.6 m CMOS process. A bias current reuse technique is employed to reduce power dissipation, and process-, voltage-, and temperature-tracking biasing techniques are used. At 900 MHz, the LNA dissipates 18 mW from a single 3 V power supply and provides 4.1 dB noise figure, 12.3 dB power gain, 00033.0 dB reverse isolation, and an input 1-dB compression level of 00016 dBm. Analysis and modeling considerations for silicon-based monolithic transformers are presented, and it is shown that a monolithic transformer occupies less die area and provides a higher quality factor than two independent inductors with the same effective inductance in differential applications. I. INTRODUCTION F INE-LINE CMOS technology easily provides high frequency active devices for use in RF applications (e...

Based on an active transmission line concept and twodimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and small-signal equivalent circuit of the MOSFET, three intrinsic noise parameters ( , , and )for the drain noise and induced gate noise are calculated. Validity and error analysis for the simulation are discussed by comparing the simulation results with theoretical results as well as measured data. Index Terms---MOSFETs, semiconductor device modeling, semiconductor device noise, simulation.

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

Short-channel CMOS technologies have shown growing prominence for a number of RF applications, such as wide-band wireless communication systems. However, the issue of excessive noise in submicron devices remains a major impediment to CMOS-based low-noise RF design. This paper expands very limited theoretical work existing in the #eld and presents new results in a form suitable for circuit design applications. We analyze the high-frequency noise behavior of a short-channel Metal-Oxide-Silicon Field-E#ect Transistor #MOSFET# in saturation within the scope of the drift-di#usion model. As a result of hot-electron e#ects in a signi#cant portion of a short channel, both drain current noise and channel-induced gate current noise turn out to be strong functions of the #eld distribution in the high-#eld region and therefore of biasing conditions. We present both #rst-principle and semi-phenomenological calculations of the noise factors and compare them with experimental results. Under the wor...