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49
A 1.5V, 1.5GHz CMOS low noise amplifier
 IEEE J. SolidState Circuits
, 1997
"... Abstract—A 1.5GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6 m CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In th ..."
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Cited by 125 (11 self)
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Abstract—A 1.5GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6 m CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices. Index Terms — Amplifier noise, induced gate noise, low noise amplifier, microwave amplifier, MOSFET amplifier, noise figure, random noise, semiconductor device noise. I.
Jitter and phase noise in ring oscillators
 IEEE Journal SolidState Circuits
, 1999
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Scaling OptoelectronicVLSI Circuits into the 21st Century: A Technology Roadmap
 IEEE J. Selected Topics in Quantum Electronics
, 1996
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Meyer "Noise in CurrentCommutating CMOS Mixers
 IEEE Journal of SolidState Circuits
, 1999
"... Abstract — A noise analysis of currentcommutating CMOS mixers, such as the widely used CMOS Gilbert cell, is presented. The contribution of all internal and external noise sources to the output noise is calculated. As a result, the noise figure can be rapidly estimated by computing only a few param ..."
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Cited by 17 (0 self)
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Abstract — A noise analysis of currentcommutating CMOS mixers, such as the widely used CMOS Gilbert cell, is presented. The contribution of all internal and external noise sources to the output noise is calculated. As a result, the noise figure can be rapidly estimated by computing only a few parameters or by reading them from provided normalized graphs. Simple explicit formulas for the noise introduced by a switching pair are derived, and the upper frequency limit of validity of the analysis is examined. Although capacitive effects are neglected, the results are applicable up to the gigahertz frequency range for modern submicrometer CMOS technologies. The deviation of the device characteristics from the ideal square law is taken into account, and the analysis is verified with measurements. Index Terms—Active mixers, analog integrated circuits, CMOS analog integrated circuits, CMOS mixers, frequency conversion, Gilbert cell, mixer noise, mixers. I.
MOS transistor modeling for RF IC design
 IEEE J. SolidState Circuits
, 2000
"... The design of radiofrequency (RF) integrated circuits (ICs) in deepsubmicron CMOS processes requires accurate and scalable compact models of the MOS transistor that are valid in the GHz frequency range and beyond. Unfortunately, the currently available compact models give inaccurate results if the ..."
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Cited by 16 (0 self)
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The design of radiofrequency (RF) integrated circuits (ICs) in deepsubmicron CMOS processes requires accurate and scalable compact models of the MOS transistor that are valid in the GHz frequency range and beyond. Unfortunately, the currently available compact models give inaccurate results if they are not modified adequately. This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical and scalable equivalent circuit that can easily be implemented as a Spice subcircuit is described. The smallsignal and noise models are discussed and measurements made on a 0.25µm CMOS process are presented that validate the RF MOST model up to 10GHz. I.
A 14b 12MS/s CMOS Pipeline ADC With Over 100dB SFDR
 IEEE Journal of SolidState Circuits
, 2004
"... analogtodigital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gainboosting technique is described. The converter is optimized for lowvoltage lowpower applications by applying an optimum stagescaling algorithm at the architectural level and an opamp and co ..."
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Cited by 10 (1 self)
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analogtodigital converter (ADC) using a passive capacitor erroraveraging technique and a nested CMOS gainboosting technique is described. The converter is optimized for lowvoltage lowpower applications by applying an optimum stagescaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18 m 6M1P CMOS process, this converter achieves a peak signaltonoise plus distortion ratio (SNDR) of 75.5 dB and a 103dB spuriousfree dynamic range (SFDR) without trimming, calibration, or dithering. With a 1MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the frontend sampleandhold circuit is achieved using bootstrapped thinoxide transistors as switches, resulting in an SFDR of 97 dB when a 40MHz fullscale input is digitized. The ADC occupies an active area of 10 mmP and dissipates 98 mW. Index Terms—Analog integrated circuits, capacitor mismatch, comparator sharing, discretetime commonmode voltage regulation, early comparison, low power, low voltage, nested CMOS gain boosting, opamp sharing, passive capacitor erroraveraging, pipeline analogtodigital converter, pseudodifferential, subsampling. I.
A design methodology for highlyintegrated lowpower receivers for wireless communications
, 2001
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Monolithic transformers and their application in a differential CMOS RF lownoise amplifier
 J. m So [10] S. ac IE vo [11] Y in m H ppP. Maligeorgos
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A new model for thermal channel noise of deepsubmicron MOSFETS and its application in RFCMOS design
 IEEE Journal of SolidState Circuits
"... In this paper we present a simple analytical model for the thermal channel noise of deep submicron MOS transistors including hot carrier effects. The model is verified by measurements and implemented in the standard BSIM3v3 SPICE model. We show that the consideration of this additional noise caused ..."
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Cited by 9 (0 self)
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In this paper we present a simple analytical model for the thermal channel noise of deep submicron MOS transistors including hot carrier effects. The model is verified by measurements and implemented in the standard BSIM3v3 SPICE model. We show that the consideration of this additional noise caused by hot carrier effects is essential for the correct simulation of the noise performance of a LNA in the GHz range.
An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs
 IEEE Trans. Electron Devices
, 2000
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