The new generation of silicon retinae has two defining characteristics. First, these synthetic retinae are morphologically equivalent to their biological counterparts---at an appropriate level of abstraction. Second, they accomplish all four major operations performed by biological retinae using neurobiological principles: (1) continuous sensing for detection, (2) local automatic gain control for amplification, (3) spatiotemporal bandpass filtering for preprocessing, and (4) adaptive sampling for quantization. I introduce the term retinomorphic to refer to this subclass of the neuromorphic electronic systems [30]. I compare and contrast their design principles with the standard practice in imager design. I argue that neurobiological principles are best suited to perceptive systems [43] that go beyond reproducing the dynamic scene, like a conventional video camera does, to extracting salient information in real time [3]. I shall present results from a fully operational retinomorphic vis...

. I describe a vision system that uses neurobiological principles to perform all four major operations found in biological retinae: #1# continuous sensing for detection, #2# local automatic gain control for ampli#cation, #3# spatiotemporal bandpass #ltering for preprocessing, and #4# adaptive sampling for quantization. All four operations are performed at the pixel level. The system includes a random-access time-division multiplexed communication channel that reads out asynchronous pulse trains from a 64#64 pixel array in the imager chip, and transmits them to corresponding locations on a second chip that has a64# 64 arrayofintegrators. Both chips are fully functional. I compare and contrast the design principles of the retina with the standard practice in imager design and analyze the circuits used to amplify, #lter, and quantize the visual signal, with emphasis on the performance trade-o#s inherent in the circuit topologies used. Keywords: retinomorphic, neuromorphic, local gain co...

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This chapter covers device and circuit aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. Low-current biasing also has a strong influence on noise and matching properties. All these issues are discussed, together with the particular aspects related to passive devices and parasitic effects. The design process has to be supported by efficient and accurate circuit simulation. To this end, the EKV compact MOST model for circuit simulation is shortly presented. The use of the basic concepts such as pinch-off voltage, inversion factor and specific current are highlighted thanks to some very simple but fundamental circuits and to an effective use of the model. New design techniques that are appropriate for low-power and/or low-voltage circuits are presented with an emphasis on the analog floating point technique, the instantaneous companding principle, and their application to filters.

This paper describes CMOS circuits that generate a wideranging set of fixed bias currents, spanning at least 6 decades down to picoamperes. A master current generated by a bootstrapped current reference is successively divided by a current splitter to generate the desired references. An unpublished startup circuit and a novel power control mechanism are described. Measurements from a 0.35u implementation are presented and nonidealities are investigated. Readers are directed to a design kit that makes it simple to generate the layout for a bias generator with a set of desired currents for scalable MOSIS CMOS processes.

Abstract—This paper considers the viability of compact low-resolution low-power mini digital-to-analog converters (mini-DACs) for use in large arrays of neural type cells, where programmable weights are required. Transistors are biased in weak inversion in order to yield small currents and low power consumptions, a necessity when building large size arrays. One important drawback of weak inversion operation is poor matching between transistors. The resulting effective precision of a fabricated array of 50 DACs turned out to be 47 % (1.1 bits), due to transistor mismatch. However, it is possible to combine them two by two in order to build calibrated DACs, thus compensating for inter-DAC mismatch. It is shown experimentally that the precision can be improved easily by a factor of 10 (4.8 % or 4.4 bits), which makes these DACs viable for low-resolution applications such as massive arrays of neural processing circuits. A design methodology is provided, and illustrated through examples, to obtain calibrated mini-DACs of a given target precision. As an example application, we show simulation results of using this technique to calibrate an array of digitally controlled integrate-and-fire neurons. Index Terms—Analog design, calibration, current splitters, digital-to-analog converters, fuzzy circuits, neural networks, subthreshold, weak inversion. I.

This paper describes an on-chip programmable bias current generator, intended for mixed signal chips requiring a wide ranging set of currents. The individual generators share a master current reference. A serial digital interface to the chip controls the biases by bits loaded into a 24-bit shift register. These bits control the steering of current from a current splitter. The summed current splitter output is actively mirrored to a broadcasted bias voltage. Measurements from an implementation in 0.35u 4M-2P CMOS show a total range of bias current of over 6 decades (>120dB) ranging from a few times the off-current up to the master reference current. For currents larger than the minimum, the generator has resolution spanning nearly its full 24 bit range (144dB), e.g. for a master current of 10uA, any bias current can be varied by as little as 0.5 pA with the caveat that the code is not guaranteed monotonic. Each bias occupies an area of 0.026 mm 2, which is about 65 % of the bonding pad that it replaces. Measured variation in generated currents is <10 % in strong inversion and about 20-30 % in weak inversion. 1.

Abstract—We present a 32 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57 % to 6.6 % (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is SV m ST m, while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35- m CMOS process. Index Terms—Address-event representation (AER), analog circuits, artifical retina, calibration, contrast computation, currentmode circuits, imagers, low-power circuits and systems, mismatch, neuromorphic circuits, sensory systems, trimming, vision systems, weak inversion circuits. I.

Abstract—In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques. The convolution processing is based on the address–event-representation (AER) technique, which is a spike-based biologically inspired image and video representation technique that favors communication bandwidth for pixels with more information. As a first test prototype, a pixel array of 16 16 has been implemented with programmable kernel size of up to 16 16. The chip has been fabricated in a standard 0.35- m complimentary metal–oxide–semiconductor (CMOS) process. The technique also allows to process larger size images by assembling 2-D arrays of such chips. Pixel operation exploits low-power mixed analog–digital circuit techniques. Because of the low currents involved (down

Abstract—In this brief, we present the “Stochastic I-Pot. ” It is a circuit element that allows for digitally programming a precise bias current ranging over many decades, from pico-amperes up to hundreds of micro-amperes. I-Pot blocks can be chained within a chip to allow for any arbitrary number of programmable bias currents. The approach only requires to provide the chip with three external pins, the use of an external current measuring instrument, and a computer. This way, once all internal I-Pots have been characterized, they can be programmed through a computer to provide any desired current bias value with very low error. The circuit block turns out to be very practical for experimenting with new circuits (specially when a large number of biases are required), testing wide ranges of biases, introducing means for current mismatch calibration, offsets compensations, etc. using a reduced number of chip pins. We show experimental results of generating bias currents with errors of 0.38 % (8 bits) for currents varying from 176 A to 19.6 pA. Temperature effects are characterized. Index Terms—Analog circuits, current-mode circuits, current biases, low-power circuits, mismatch, programmable current sources, reference currents. I.