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20
Feedback shift registers, 2adic span, and combiners with memory
 Journal of Cryptology
, 1997
"... Feedback shift registers with carry operation (FCSR’s) are described, implemented, and analyzed with respect to memory requirements, initial loading, period, and distributional properties of their output sequences. Many parallels with the theory of linear feedback shift registers (LFSR’s) are presen ..."
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Cited by 50 (7 self)
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Feedback shift registers with carry operation (FCSR’s) are described, implemented, and analyzed with respect to memory requirements, initial loading, period, and distributional properties of their output sequences. Many parallels with the theory of linear feedback shift registers (LFSR’s) are presented, including a synthesis algorithm (analogous to the BerlekampMassey algorithm for LFSR’s) which, for any pseudorandom sequence, constructs the smallest FCSR which will generate the sequence. These techniques are used to attack the summation cipher. This analysis gives a unified approach to the study of pseudorandom sequences, arithmetic codes, combiners with memory, and the MarsagliaZaman random number generator. Possible variations on the FCSR architecture are indicated at the end. Index Terms – Binary sequence, shift register, stream cipher, combiner with memory, cryptanalysis, 2adic numbers, arithmetic code, 1/q sequence, linear span. 1
Structured Redundancy for Fault Tolerance in LTI StateSpace Models and Petri Nets
 Kybernetika
, 1999
"... The design and implementation of dynamic systems has traditionally focused on minimal representations which require the least number of state variables. However, \structured redundancy"  redundancy that has been intentionally introduced in some systematic way  can be extremely important when fault ..."
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Cited by 9 (9 self)
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The design and implementation of dynamic systems has traditionally focused on minimal representations which require the least number of state variables. However, \structured redundancy"  redundancy that has been intentionally introduced in some systematic way  can be extremely important when fault tolerance is desired. The redundancy can be used to detect and correct errors or to guarantee desirable performance despite hardware or computational failures. Modular redundancy, the traditional approach to fault tolerance, is prohibitively expensive because of the overhead in replicating the hardware. This paper discusses alternative methods for systematically introducing redundancy in dynamic systems. Our approach consists of mapping the state space of the original system into a redundant space of higher dimension while preserving the properties of the original system in some encoded form within this larger space. We illustrate our approach by focusing on linear timeinvariant (LTI) dyna...
On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers
 IEEE Trans. on VLSI Systems
, 1993
"... The effectiveness of residue code checking for online error detection in parallel two's complement multipliers has up to now only been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it i ..."
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Cited by 5 (0 self)
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The effectiveness of residue code checking for online error detection in parallel two's complement multipliers has up to now only been evaluated experimentally for few architectures. In this paper a formal analysis is given for most of the current multiplication schemes. Based on this analysis it is shown which check bases are appropriate, and how the original scheme has to be extended for complete error detection at the input registers and Booth recoding circuitry. In addition, we argue that the hardware overhead for checking can be reduced by approximately one half if a small latency in error detection is acceptable. Schemes for structuring the checking logic in order to guarantee it to be selftesting, and thus achieve the totally selfchecking goal for the overall circuit, are also derived. 1 Introduction One of the most important parallel algorithms which is part of nearly every computer system is fast multiplication. Methods for online error detection in parallel multipliers ...
A MULTILEVEL VIEW OF DEPENDABLE COMPUTING
, 1994
"... This paper serves a dual purpose. It presents a unified framework and terminology for the study of computer system dependability. It also surveys the field of dependable computing in light of the proposed framework. Specifically, impairments to dependability are viewed from six levels, each being m ..."
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Cited by 4 (1 self)
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This paper serves a dual purpose. It presents a unified framework and terminology for the study of computer system dependability. It also surveys the field of dependable computing in light of the proposed framework. Specifically, impairments to dependability are viewed from six levels, each being more abstract than the previous one. It is argued that all of these levels are useful, in the sense that proven dependability assurance techniques can be applied at each level, and that it is beneficial to have distinct, precisely defined terminology for describing impairments to, and procurement strategies for, computer system dependability at these levels. The six levels are: (I) Defect level or component level, dealing with deviant atomic parts. (2) Fault level or logic level, dealing with deviant signal values or path selections. (3) Error level or information level, dealing with deviant data or internal states. (4) Malfunction level or system level, dealing with deviant functional behavior. (5) Degradation level or service level, dealing with deviant performance. (6) Failure level or result level, dealing with deviant outputs or actions. Briefly, a hardware or software component may be defective (hardware may also become defective due to wear and aging). Certain system states will expose the defect, resulting in the development of faults
ParityPreserving Transformations in Computer Arithmetic
 Proc. SPIE Conf. Advanced Signal Processing Algorithms, Architectures, and Implementations XII
, 2002
"... Parity checking comprises a lowredundancy method for the design of reliable digital systems. While quite effective for detecting singlebit transmission or storage errors, parity encoding has not been widely used for checking the correctness of arithmetic results because parity is not preserved dur ..."
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Cited by 3 (1 self)
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Parity checking comprises a lowredundancy method for the design of reliable digital systems. While quite effective for detecting singlebit transmission or storage errors, parity encoding has not been widely used for checking the correctness of arithmetic results because parity is not preserved during arithmetic operations and parity prediction requires fairly complex circuits in most cases. We propose a general strategy for designing paritychecked arithmetic circuits that takes advantage of redundant intermediate representations. Because redundancy is often used for high performance anyway, the incremental cost of our proposed method is quite small. Unlike conventional binary numbers, redundant representations can be encoded and manipulated in such a way that parity is preserved in each step. Additionally, lack of carry propagation ensures that the effect of a fault is localized rather than catastrophic. After establishing the framework for our paritypreserving transformations in computer arithmetic, we illustrate some applications of the proposed strategy to the design of paritychecked adder/subtractors, multipliers, and other arithmetic structures used in signal processing.
Encoded Dynamics for Fault Tolerance in Linear FiniteState Machines
 IEEE Transactions on Automatic Control
, 2002
"... Modular redundancy, the traditional approach to fault tolerance, is prohibitively expensive because of the overhead in replicating the hardware. In this paper we discuss fault tolerance in linear finitestate machines (LFSM's) and present a range of alternatives to modular redundancy. Our approach r ..."
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Cited by 3 (1 self)
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Modular redundancy, the traditional approach to fault tolerance, is prohibitively expensive because of the overhead in replicating the hardware. In this paper we discuss fault tolerance in linear finitestate machines (LFSM's) and present a range of alternatives to modular redundancy. Our approach replaces a given LFSM with a larger, redundant one that preserves the state, evolution and properties of the original LFSM, perhaps in some linearly encoded form. The encoded state of the larger LFSM allows an external mechanism to perform error detection and correction by identifying and analyzing violations of the code restrictions. For a given LFSM and a given linear coding scheme, we completely characterize the class of appropriate redundant machines and illustrate how error detection and correction can be performed using techniques already developed in the communications setting. The existence of the class of redundant machines is a possibility that was not considered in previous work; we illustrate the consequences and applications of our approach through examples.
FaultTolerant Computation in Groups and Semigroups: Applications to Automata, Dynamic Systems and Petri Nets
"... The traditional approach to faulttolerant computation has been via modular hardware redundancy. ..."
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Cited by 2 (1 self)
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The traditional approach to faulttolerant computation has been via modular hardware redundancy.
Hardware Assisted Preemptive Control Flow Checking for Embedded Processors to
 Improve Reliability.” International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). Seoul, Korea
, 2006
"... Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed softwareonly approaches suffer from significant code size penalties, resulting in poor performance. Proposed hardwareassisted approaches are not scala ..."
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Cited by 2 (0 self)
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Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed softwareonly approaches suffer from significant code size penalties, resulting in poor performance. Proposed hardwareassisted approaches are not scalable and therefore cannot be i m pl ement ed i n r eal embedded s yst ems. T hi s paper pr esent s a scalable, cost effective and novel fault detection technique, to ensure proper control flow of a program. This technique includes architectural changes to the processor and software modifications.
FaultTolerant Sequence Enumerators
 In Proceedings of MED 2000, the 8th IEEE Mediterranean Conf. on Control and Automation
, 2000
"... Modular redundancy, the traditional approach to fault tolerance, is prohibitively expensive because of the overhead in replicating the hardware. In this paper we discuss alternative techniques for fault tolerance in sequence enumerators that are implemented as linear finitestate machines (LFSM's). ..."
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Cited by 1 (1 self)
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Modular redundancy, the traditional approach to fault tolerance, is prohibitively expensive because of the overhead in replicating the hardware. In this paper we discuss alternative techniques for fault tolerance in sequence enumerators that are implemented as linear finitestate machines (LFSM's). Our approach replaces a given LFSM with a larger, redundant LFSM that preserves the evolution and properties of the original one. The state of the larger LFSM is a linearly encoded version of the state in the original machine and allows an external mechanism to perform error detection and correction by identifying and analyzing violations of the code restrictions. In this paper, we characterize the class of appropriate redundant LFSM's and demonstrate a variety of possibilities for fault tolerance, ranging from no redundancy to full replication.
A HighLevel Synthesis Approach to Optimum Design of SelfChecking Circuits
, 1996
"... We present an innovative solution to design of selfchecking systems implementing arithmetic algorithms. Rather than substituting selfchecking units in system synthesized independently of selfchecking requirements, we introduce selfchecking in highlevel synthesis as a requirement already for sche ..."
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Cited by 1 (0 self)
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We present an innovative solution to design of selfchecking systems implementing arithmetic algorithms. Rather than substituting selfchecking units in system synthesized independently of selfchecking requirements, we introduce selfchecking in highlevel synthesis as a requirement already for scheduling the DFG. Rules granting error detection allow optimum partitioning of the DFG; minimumlatency, resourceconstrained scheduling is performed with the support of such partitioning so as to optimize the number of checkers as well as that of other resources.