Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space [30]. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tri-state on-chip buses with level or transition signalin...

The imminent convergence of computer, communications, and consumer electronic products and market implies a need for optimization intensive techniques for synthesis of low power hard real-time systems. In this paper, we present a system-level approach for power minimization under a set of userspecified costs and timing constraints of hard real-time designs. The approach simultaneously optimizes all three degrees of freedom for power minimization, namely switching activity, effective capacity and voltage supply. We first define two key associated optimization problems, processor allocation and task assignment, and establish their computational complexity. Next, we describe a novel meta-algorithmics algorithm development strategy. The strategy is used for evaluation and statistical validation of the key parameters that guide the heuristic assignment process. The statistical analysis of comprehensive experimental results and their comparison with the developed conservative and optimistic ...

In this paper we reflect on the nature of digital telecommunication systems. We argue that these systems require, by nature, a heterogeneous specification and an implementation with heterogeneous architectural styles. CoWare is a hardware/software co-design environment based on a data model that allows to specify, simulate, and synthesize heterogeneous hardware/software architectures from a heterogeneous specification. CoWare is based on the principle of encapsulation of existing hardware and software compilers and special attention is paid to the interactive synthesis of hardware/software and hardware/hardware interfaces. The principles of CoWare will be illustrated by the design process of a spread-spectrum receiver for a pager system. I.

informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a category of processors that are programmable yet optimized to reduce power consumption for a specific set of applications.

The advent of portable and high-density devices has made power consumption a critical design concern. In this paper, we address the problem of reducing power consumption via gate-level voltage scaling for those designs that are not under the strictest timing budget. We first use a maximum-weighted independent set formulation for voltage reduction on non-critical part of the circuit. Then, we use a minimum-weighted separator set formulation to do gate sizing and integrate the sizing procedure with a voltage scaling procedure to enhance power saving on the whole circuit. The proposed methods are evaluated using the MCNC benchmark circuits. and an average of 19.12 % power reduction over the circuits having only one supply voltage has been achieved. 1

We develop an approach to minimizing power consumption of portable wireless DSP applications using a set of compilation and architectural techniques. The key technical innovation is a novel divide-and-conquer compilation technique to minimize the number of operations for general DSP computations. Our technique optimizes not only a significantly wider set of computations than the previously published techniques, but also outperforms (or performs at least as well as other techniques) on all examples. Along the architectural dimension, we investigate coordinated impact of compilation techniques on the number of processors which provide optimal trade-off between cost and power. We demonstrate that proper compilation techniques can significantly reduce power with bounded hardware cost. The effectiveness of all techniques and algorithms is documented on numerous real-life designs.

Interest in low power embedded systems has increased considerably in the past few years. To produce low power code and to allow an estimation of power consumption of software running on embedded systems, a power model was developed based on physical measurement using an evaluation board and integrated into a compiler and profiler. The compiler uses the power information to choose instruction sequences consuming less power, whereas the profiler gives information about the total power consumed during execution of the generated program. The used compiler is parameterized such that e.g. the register file size may be changed. The resulting code is evaluated with respect to code size, performance and power consumption for different register file sizes. The extracted information is especially useful during application analysis and architecture space exploration in ASIP design. Our analysis gives the designer the ability to estimate the desirable register file size for an ASIP design. The size of the register file should be considered as a design parameter since it has a strong impact on the energy consumption of embedded systems.

In low power design for deep submicron and nanometer regimes, the peak power, power fluctuation, average power and total energy are equally design constraints. In this work, we propose datapath scheduling algorithms for simultaneous minimization of peak and average power. The minimization schemes based on integer linear programming (ILP) are developed for the design of datapaths that can function in three modes of operation: (1) single supply voltage and single frequency (SVSF), (2) multiple supply voltages and dynamic frequency clocking (MVDFC) and (3) multiple supply voltages and multicycling (MVMC). The techniques are evaluated by estimating the peak power consumption, the average power consumption and the power delay product of selected high level synthesis benchmark circuits for different resource constraints. Experimental results indicate that combining multiple supply voltages and dynamic frequency clocking, yields significant reductions in the peak power, the average power, and the power delay product.

In this work we present generic low power techniques for minimizing the energy-delay product for CMOS digital circuits. These techniques, which optimize and use multiple or variable power supply and threshold voltages and transistor sizing, are presented according to their application to different classes of circuits along the space and time dimensions.