In this paper the fundamental electrical limits of MOSFETs are discussed and modeled to predict the scaling limits of digital bulk CMOS circuits. Limits discussed include subthreshold leakage, short channel effects (SCE), gate induced drain leakage (GIDL), gate tunneling current, time dependent dielectric breakdown (TDDB), and hot carrier effects (HCE). This paper predicts the scaling of bulk CMOS MOSFETs for high performance microprocessors to reach its limits at drawn lengths of approximately 0:08¯m. Trends in scaling interconnects are also discussed. The device limits presented are used to project the characteristics of future processor technologies and to find scaling factors for the SPICE level 3 model parameters. A SPICE device model which can be scaled to reflect a range of MOSFET technologies from drawn lengths of 0:5¯m to 0:1¯m is presented along with a scalable wire model. Key Words and Phrases: MOSFET, device scaling, interconnect scaling, subthreshold leakage, short channel...

An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequencydomain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with symbolic results, both obtained with this method, insight into the nonlinear operation of analog integrated circuits can be gained. For accurate distortion computations, the accuracy of the transistor models is critical. A MOS transistor model is discussed that allows us to explain the measured fourth-order nonlinear behavior of a 1-GHz CMOS upconverter. Further, the method is illustrated with several examples, including the analysis of an operational amplifier up to its gain-bandwidth product. This example has also been verified experimentally. Index Terms---Analog integrated circuits, harmonic distortion, nonlinear ...

In this work we present generic low power techniques for minimizing the energy-delay product for CMOS digital circuits. These techniques, which optimize and use multiple or variable power supply and threshold voltages and transistor sizing, are presented according to their application to different classes of circuits along the space and time dimensions.