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Power Minimization in IC Design: Principles and Applications
 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1996
"... Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low powe ..."
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Cited by 187 (29 self)
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Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
HighLevel Power Modeling, Estimation, and Optimization
 IEEE Trans. On Computer Aided Design
, 1998
"... Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the othe ..."
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Cited by 103 (12 self)
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Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital verylargescaleintegration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand highspeed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of highend products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of lowpower VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.
Power Macromodeling for High Level Power Estimation
, 1997
"... A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching activity. The resulting power macromodel, consisting of a single three dimensional table, can be used to estimate the power consumed in the cir ..."
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Cited by 68 (9 self)
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A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching activity. The resulting power macromodel, consisting of a single three dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a lowlevel (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. In contrast to other proposed techniques, this can be done for any given logic circuit without any user intervention, and applies to all possible input/output signal statistics; it does not require one to construct specialized analytical equations for the power dissipation. The three dimensions of our tablebased model are the average input signal probability, average input transition density, and average output zerodelay transition density. This approach has been implemented and models...
RegisterTransfer Level Estimation Techniques for Switching Activity and Power Consumption
 in Proc. Int. Conf. ComputerAided Design
, 1996
"... We present techniques for estimating switching activity and power consumption in registertransfer level (RTL) circuits. Previous work on this topic has ignored the presence of glitching activity at various data path and control signals, which can lead to significant underestimation of switching act ..."
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Cited by 48 (4 self)
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We present techniques for estimating switching activity and power consumption in registertransfer level (RTL) circuits. Previous work on this topic has ignored the presence of glitching activity at various data path and control signals, which can lead to significant underestimation of switching activity. For data path blocks that operate on wordlevel data, we construct piecewise linear models that capture the variation of output glitching activity and power consumptionwith various wordlevel parameters like mean, standard deviation, spatial and temporal correlations, and glitching activity at the block's inputs. For RTL blocks that operate on data that need not have an associated wordlevel value, we present accurate bitlevel modeling techniques for glitching activity as well as power consumption. This allows us to perform accurate power estimation for controlflow intensive circuits, where most of the power consumed is dissipated in nonarithmetic components like multiplexers, regi...
On Gate Level Power Optimization Using DualSupply Voltages
 IEEE Trans. on VLSI Systems
, 2001
"... In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technologymapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed ..."
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Cited by 35 (3 self)
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In this paper, we present an approach for applying two supply voltages to optimize power in CMOS digital circuits under the timing constraints. Given a technologymapped network, we first analyze the power/delay model and the timing slack distribution in the network. Then a new strategy is developed for timingconstrained optimization issues by making full use of slacks. Based on this strategy, the power reduction is translated into the polynomialtimesolvable maximalweightedindependent set problem on transitive graphs. Since different supply voltages used in the circuit lead to totally different power consumption, we propose a fast heuristic approach to predict the optimum dualsupply voltages by looking at the lower bound of power consumption in the given circuit. To deal with the possible power penalty due to the level converters at the interface of different supply voltages, we use a "constrained FM" algorithm to minimize the number of level converters. We have implemented our approach under SIS environment. Experiment shows that the resulting lower bound of power is tight for most circuits and that the predicted "optimum" supply voltages are exactly or very close to the best choice of actual ones. The total power saving of up to 26% (average of about 20%) is achieved without degrading the circuit performance, compared to the average power improvement of about 7% by gate sizing technique based on a standard cell library. Our technique provides the powerdelay tradeoff by specifying different timing constraints in circuits for power optimization.
HighLevel Area and Power Estimation for VLSI Circuits
, 1997
"... This paper addresses the problem of computing the area complexity of a multioutput combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the ..."
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Cited by 34 (4 self)
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This paper addresses the problem of computing the area complexity of a multioutput combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the given multioutput Boolean function description into an equivalent singleoutput function. The model is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. Highlevel power estimates based on the total capacitance estimates and average activity estimates are also presented.
Scheduling and Resource Binding for Low Power
 in Proceedings of the IEEE International Symposium on System Synthesis
, 1995
"... Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resourcebinding steps of highlevel synthesis. Algorithms for th ..."
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Cited by 28 (0 self)
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Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resourcebinding steps of highlevel synthesis. Algorithms for these steps targeting at lowpower datapaths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the functional units (adders, multipliers) by minimizing the transitions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall datapath power budget. 1 Introduction Current VLSI technology allows circuits with more and more functionality to be integrated in just one chip. Nowadays, portable applications are not only wrist clocks or calculators but multimedia terminals, mobile telephones and other realtime systems. These new applications are based on intensive ...
A mathematical basis for powerreduction in digital VLSI systems
 IEEE Trans. CAS Part II
, 1997
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Power Modeling for High Level Power Estimation
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2000
"... In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single fourdimensional table, can be used to estimate the power consu ..."
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Cited by 25 (1 self)
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In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single fourdimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a lowlevel (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our tablebased model are the average input signal probability, average input transition density, average spatial correlation coe#cient and average output zerodelay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one...
Power Estimation Techniques for Integrated Circuits
, 1995
"... With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a co ..."
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Cited by 19 (0 self)
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With the advent of portable and highdensity microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: I the use of simplified delay models, and 2 modeling t 1 e longterm behavior of logic signals wit I! probabilities. The array of available techniques diger in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the diflerent assumptions on which these techniques are based, and the impact of these assumptions on their accuracy and speed.