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48
Low Voltage Analog Circuit Design Techniques: A Tutorial
, 2000
"... Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In particular, (i) technology considerations; (ii) transistor model capable to provide performance and power tradeoffs; (iii) low voltage implementation techniques capable to reduce the power supply requirements, such ..."
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Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In particular, (i) technology considerations; (ii) transistor model capable to provide performance and power tradeoffs; (iii) low voltage implementation techniques capable to reduce the power supply requirements, such as bulkdriven, floatinggate, and selfcascode MOSFETs; (iv) basic LV building blocks; (v) multistage frequency compensation topologies; and (vi) fullydifferential and fullybalanced systems.
Consistent noise models for analysis and design of CMOS circuits
 IEEE Trans.Circuits & Systems I
"... Abstract—Simple, physicsbased MOSFET noise models, valid over the linear, saturation, and subthreshold operation regions are presented. The consistency of the models representing series–parallel associations of transistors is verified. Simple formulas for hand analysis using the inversion level co ..."
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Abstract—Simple, physicsbased MOSFET noise models, valid over the linear, saturation, and subthreshold operation regions are presented. The consistency of the models representing series–parallel associations of transistors is verified. Simple formulas for hand analysis using the inversion level concept are developed. The proportionality between the flicker noise corner frequency and the transistor transition frequency is proved and experimentally verified under wide bias conditions. Application of the noise models to a lownoise design is shown. Index Terms — 1 noise, compact modeling, lownoise design, MOSFET, noise.
Automated design of operational transconductance amplifiers using reversed geometric programming
 In Proceedings of the 41th IEEE/ACM Design Automation Conference
, 2004
"... We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and nonconvex constraints. Adding a limited set of nonconvex constraints can improve the accuracy of convex equationbased optimizati ..."
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Cited by 5 (0 self)
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We present a method for designing operational amplifiers using reversed geometric programming, which is an extension of geometric programming that allows both convex and nonconvex constraints. Adding a limited set of nonconvex constraints can improve the accuracy of convex equationbased optimization, without compromising global optimality. These constraints allow increased accuracy for critical modeling equations, such as the relationship between gm and IDS. To demonstrate the design methodology, a foldedcascode amplifier is designed in a 0.18 µm technology for varying speed requirements and is compared with simulations and designs obtained from geometric programming. Categories and Subject Descriptors:
Improvements in biasing and compensation of CMOS opamps
 in 2004 Intl. Symposium on Circuits and Systems (ISCAS 2004
, 2004
"... In this paper, we present modifications to the constantgm bias circuit and the Millerlead compensation technique which eliminate or minimize some of their shortcomings. First, we demonstrate how parasitic pad capacitance can cause instability in the constantgm bias circuit, and show that the tran ..."
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In this paper, we present modifications to the constantgm bias circuit and the Millerlead compensation technique which eliminate or minimize some of their shortcomings. First, we demonstrate how parasitic pad capacitance can cause instability in the constantgm bias circuit, and show that the transconductance is constant only for specific bias conditions. Next, we suggest a new circuit topology that requires 75% less compensation capacitance to achieve stability. We also discuss problems with Millerlead compensation that arise from temperature, process, and load variations. Finally, we present a new biasing technique to correct these problems, and, through simulation, demonstrate a 40º improvement in phase margin over load current variations. 1.
FloatingGate Analog Implementation of the Additive SoftInput SoftOutput Decoding Algorithm
"... Abstract—The softinput softoutput algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multipleinput floatinggate C ..."
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Abstract—The softinput softoutput algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multipleinput floatinggate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results. Index Terms—Analog processing, floatinggate (FG) MOS transistors, parallel concatenated convolutional codes (PCCC), soft input soft output (SISO), translinear circuits, turbo codes. I.
Floating gate analog implementation of the additive softinput softoutput decoding algorithm
 Proc. 2002 IEEE Int. Symp. Circuits and Systems
, 2002
"... ..."
MOSVIEW: A Graphical Tool for MOS Analog Design
"... This paper presents MOSVIEW, a graphical tool for transistorlevel design of analog MOS circuits. MOSVIEW allows students to visualize and explore the design space in order to size and bias the transistor for a given set of specifications. 1. ..."
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This paper presents MOSVIEW, a graphical tool for transistorlevel design of analog MOS circuits. MOSVIEW allows students to visualize and explore the design space in order to size and bias the transistor for a given set of specifications. 1.
Wolf: presentation at the
 CERN Workshop on Intermittency
, 1991
"... et codirigée par Agnès FRONT préparée au sein du Laboratoire d’Informatique de Grenoble et de l’Ecole Doctoral de “Mathématiques, Sciences et Technologies de l’Information, Informatique” Modélisation intentionnelle et organisationnelle des systèmes d’information dans les organisations virtuelles Thè ..."
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et codirigée par Agnès FRONT préparée au sein du Laboratoire d’Informatique de Grenoble et de l’Ecole Doctoral de “Mathématiques, Sciences et Technologies de l’Information, Informatique” Modélisation intentionnelle et organisationnelle des systèmes d’information dans les organisations virtuelles Thèse soutenue publiquement le 13 avril 2011
FIXEDCURRENT METHOD FOR PROGRAMMING LARGE FLOATINGGATE ARRAYS
"... Speed and Accuracy of programming large floating gate array is limited by precision of current measurement and pulse generator. In this paper a novel floating gate programming method is proposed which alleviates the requirement of accurate measurement and facilitates fast programming. As opposed to ..."
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Speed and Accuracy of programming large floating gate array is limited by precision of current measurement and pulse generator. In this paper a novel floating gate programming method is proposed which alleviates the requirement of accurate measurement and facilitates fast programming. As opposed to conventional approaches this method programs fixed value of currents onto the floating gate transistor at variable control gate votlage. The technique is used in conjuction with a coarse programming method, that utilizes the positive feedback nature of pFET injection to improve the speed of programming. Measured results from an array of floating gate cells, fabricated in a 0.5µm CMOS process demonstrate the effectiveness of this method to program currents in the order of few picoamperes with approximately 8bits of resolution. 1.
A compact model of mosfet mismatch for circuit design,” SolidState Circuits
 IEEE Journal of
, 2005
"... Abstract—This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operatio ..."
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Abstract—This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 m technology confirm the accuracy of our mismatch model under various bias conditions. Index Terms—MOSFET, analog design, matching, mismatch, compact models. I.