This report consists of two major portions. First is the presentation of a methodology for measuring the performance of supercomputers. This includes a set of thirteen Fortran programs that total well over 50,000 lines of source code. They represent applications in a number of areas of engineering and scientific computing, and in many cases they represent codes that are currently used by a number of computational research and development groups. We also present the PERFECT Fortran standard which is simply a set of guidelines that allow portability to a number of types of machines. Furthermore, we present some performance measures and a methodology for recording and sharing results among a group of diverse users on different machines. The second portion of the paper presents some of the results we have obtained over the past year and a half. The results should not be used to compare machines, except in a very preliminary sense. Rather, the results are presented to show how the methodolo...

Faikenhainer, B. and K.D. Forbus, Compositional modeling: finding the right model for the job, Artificial Intelligence 51 ( 1991 ) 95-143.

This paper describes a novel strategy for generating accurate black-box models of datapath power consumption at the architecture level. This is achieved by recognizing that power consumption in digital circuits is affected by activity, as well as physical capacitance. Since existing strategies characterize modules for purely random inputs, they fail to account for the effect of signal statistics on switching activity. The Dual Bit Type (DBT) model, however, accounts not only for the random activity of the least significant bits (LSB’s), but also for the correlated activity of the most significant bits (MSB’s), which contain two’s-complement sign information. The resulting model is parameterizable in terms of complexity factors such as word length and can be applied to a wide variety of modules ranging from adders, shifters, and multipliers to register files and memories. Since the model operates at the register transfer level (RTL), it is orders of magnitude faster than gate- or circuit-level tools, but while other architecture-level techniques often err by 50-100 % or more, the DBT method offers error rates on the order of 10-15%.

This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.

In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we first present the Deferred-Merge Embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength. The algorithm always yields exact zero skew trees with respect to the appropriate delay model. Experimental results show an 8% to 15% wirelength reduction over previous constructions in [17] [18]. The DME algorithm may be applied to either the Elmore or linear delay model, and yields optimal total wirelength for linear delay. DME is a very fast algorithm, running in time linear in the number of synchronizing elements. We also present a unified BB+DME algorithm, which constructs a clock tree t...

A novel current-estimation approach is developed to support the analysis of electromigration failures in power supply and ground busses of CMOS VLSI circuits. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. As such, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST which has shown excellent accuracy and dramatic speedups compared to traditional approaches. We describe the approach and its implementation, and present the results of numerous CREST runs on real circuits. F. Najm is now with the VLSI Design Laboratory, Texas Instruments Inc., Dallas, Texas 75265 This work was supported by Texas Instruments Incorporated, and the US Air Force Rome Air Development Center. 1 Introduction The reliability of integrated circuits is a major conc...

The switch-level model represents a digital metal-oxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network state. This analysis supports the same class of networks as the switch-level simulator MOSSIM II and provides the same functionality, including the handling of bidirectional e ects and indeterminate (X) logic values. In the worst case, the analysis of an n node network can yield a set of formulas containing a total of O(n 3) operations. However, all but a limited set of dense, pass-transistor networks give formulas with O(n) total operations. The analysis can serve as the basis of e cient programs for a variety oflogic design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test generation, and symbolic veri cation.

: This paper addresses the problem of estimating, from a behavioral level description, the power consumed by a design. We propose a combination of analytical and stochastic estimation techniques and present comparisons with an architectural level power estimation tool. Average errors of about 20% have been obtained. Based on these estimates, an exploration tool, Explore, has been built to quickly scan the design space and provide estimates of performance metrics such as area and power as guidelines for selection of computational structures and high level design parameters. 1. Introduction High level synthesis has aroused considerable interest in the recent years. While a lot of effort has been put into synthesis for speed and area, power optimization has been explored only recently. Estimation of power consumption of a design is the first step towards integrating power minimization techniques into any synthesis system. Work on power estimation has been done at several different level...

Scientists are faced with a dilemma: Either they can write abstract programs that express their understanding of a problem, but which do not execute efficiently; or they can write programs that computers can execute efficiently, but which are difficult to write and difficult to understand. We have developed a compiler that uses partial evaluation and scheduling techniques to provide a solution to this dilemma.

Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on the grid reduces noise margin and increases gate delay, resulting in a serious performance impact. Checking the integrity of the supply voltage using traditional circuit simulation is not practical, for reasons of time and memory complexity. We propose a novel multigrid-like technique for the analysis of power grids. The grid is reduced to a coarser structure, and the solution is mapped back to the original grid. Experimental results show that the proposed method is very e#cient as well as suitable for both DC and transient analysis of power grids.