We propose a new R-tree structure that outperforms all the older ones. The heart of the idea is to facilitate the deferred splitting approach in R-trees. This is done by proposing an ordering on the R-tree nodes. This ordering has to be 'good', in the sense that it should group 'similar' data rectangles together, to minimize the area and perimeter of the resulting minimum bounding rectangles (MBRs). Following [19] we have chosen the so-called '2D-c' method, which sorts rectangles according to the Hilbert value of the center of the rectangles. Given the ordering, every node has a welldefined set of sibling nodes; thus, we can use deferred splitting. By adjusting the split policy, the Hilbert R-tree can achieve as high utilization as desired. To the contrary, the R -tree has no control over the space utilization, typically achieving up to 70%. We designed the manipulation algorithms in detail, and we did a full implementation of the Hilbert R-tree. Our experiments show that the '2-to-...

Computer vision algorithms are natural candidates for high performance computing due to their inherent parallelism and intense computational demands. For example, a simple 3 x 3 convolution on a 512 x 512 gray scale image at 30 frames per second requires 67.5 million multiplications and 60 million additions to be performed in one second. Computer vision tasks can be classified into three categories based on their computational complexity andcommunication complexity: low-level, intermediate-level and high-level. Special-purpose hardware provides better performance compared to a general-purpose hardware for all the three levels of vision tasks. With recent advances in very large scale integration (VLSI) technology, an application specific integrated circuit (ASIC) can provide the best performance in terms of total execution time. However, long design cycle time, high development cost and inflexibility of a dedicated hardware deter design of ASICs. In contrast, field programmable gate arrays (FPGAs) support lower design verification time and easier design adaptability atalower cost. Hence, FPGAs with an array of reconfigurable logic blocks canbevery useful compute elements. FPGA-based custom computing machines are

A discussion of convergence acceleration techniques as they relate to computational fluid dynamics problems on unstructured meshes is given. Rather than providing a detailed description of particular methods, the various different building blocks of current solution techniques are discussed and examples of solution strategies using one or several of these ideas are given. Issues relating to unstructured grid CFD problems are given additional consideration, including suitability of algorithms to current hardware trends, memory and cpu tradeoffs, treatment of non-linearities, and the development of efficient strategies for handling anisotropy-induced stiffness. The outlook for future potential improvements is also discussed.

this paper are defined in this section. A CPU is the central processing unit of a computer. The terms node, computer, machine and host are used to mean a device attached to the network, most often a computer. Nodes can be identified by a single network address, and they differ from CPUs in that it is possible for one node to have multiple CPUs. A task is a single vision operation, e.g. edge detection, segmentation, Hough transform, etc. A job is the work performed by the system in response to a user's request. A user may specify his requirement in the form of a high-level goal or a detailed plan. For example, a goal may be to identify all the objects in an outdoor scene. It can be given to the system as a high-level query which the system must use to produce a plan that can be executed to achieve the goal. Alternatively, the user can provide the plan which consists of a set of tasks that can achieve the goal. Thus, a job is created to achieve a high-level goal and is represented by a plan which consists of an ordered set of tasks

We present the design of the GFDL ocean circulation model as adapted for simulations of the Mediterranean basin for the Cedar multicluster architecture. The model simulates the basic aspects of large-scale, baroclinic ocean circulation, including treatment of irregular bottom topography. The data and computational mapping strategies and their effect on the design are discussed. The code was parameterized to offer several choices for data partitionings of the computational domain, for placement strategies for the data in the memory hierarchy, and for the number of clusters and processors used in the computational hierarchy of Cedar. The experiments and performance trends are discussed. Using four clusters and 32 processors the code demonstrates significant speedup compared to a single cluster and compared to a single processor. 1 Introduction The numerical modeling of ocean circulation is a task of great importance, both in its own right, as well as a component of climate studies. Num...

Architecture for the Support of High Performance Computing” was sponsored by the National Science Foundation to identify critical research topics in computer architecture as they relate to high performance computing. Following a wide-ranging discus-sion of the computational characteristics and requirements of the grand challenge applications, the workshop identified four major computer architecture grand challenges as crucial to advancing the state of the art of high performance computation in the coming decade. These are: (1) idealized parallel computer models; (2) usable peta-ops (1015 ops) performance; (3) computers in an era of HDTV, gigabyte networks, and visualization; and (4) infrastruc-ture for prototyping architectures. This report overviews some of the demands of the grand challenge applications and presents the above four grand challenges for computer architecture. Q MZ AM-demic Press, Inc. A. Origin of the Workshop

The premise of this paper is the observation that the engineering community in general, and the NASA aeronautics program in particular, have not been active participants in the renewed interest in high performance computing at the national level. Advocacy for high performance computing has increasingly been taken up by the science community with the argument that computational methods are becoming a third pillar of scientific discovery alongside theory and experiment. Computational engineering, on the other hand, has continually been relegated to a set of mature software tools which run on commodity hardware, with the notion that engineering problems are not complex enough to warrant the deployment of state-of-the-art hardware on such a vast scale. We argue that engineering practices can benefit equally from an aggressive program in high performance computational methods, and that these problems are at least as important as science problems, particularly with regards to any national competitiveness agenda. Because NASA aeronautics has historically been a principal driver of computational engineering research and development, the current situation represents an opportunity for the NASA aeronautics program to resume its role as a leading advocate for high performance computational engineering at the national level. We outline a sample set of Grand Challenge problems which are used to illustrate the potential benefits a reinvigorated program could produce, and use these examples to identify critical barriers to progress and required areas of investment. We conclude by noting that other communities have spent significant efforts in formulating the case for increased investment in high performance computing activities, and that a similar roadmap will be required for the engineering community. I.

OF PH.D. DISSERTATION DISTRIBUTED RUNTIME SUPPORT FOR TASK AND DATA MANAGEMENT High-performance computer architectures are evolving into larger and faster systems and, in particular, distributed memory multiprocessors represent the most powerful class of computers built today. Their available resources provide a programmer with the potential for exploiting massive amounts of parallelism in an application, and yet support for highlevel programming languages on these machines is sparse. Thus the need is great for software systems that can free the programmer from the implementation details of an architecture. This dissertation focuses on the design of software support for a high-level functional language on conventional distributed memory multiprocessors. Specifically, we present the design and implementation of a runtime system that provides implicit support for both thread management and data management, and study the effects of latency avoidance and latency tolerance on a set of sampl...

Abstract—Advancements in medicine and health care are being significantly influenced by the exploding information technology developments. The IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE will address the applications and the infrastructure innovations that would harness biomedical and health care programs in the 21st century.

We advocate a data-flow approach to data-parallelism to ensure both parallelism expressiveness and efficient exploitation of data-parallel applications on new massively parallel architectures. The rational of this approach is introduced in the first part of the paper. Then we develop an experimental language following these lines and sketch the techniques used to compile such a data-flow data-parallel language. Its compilation, based upon a static execution model enabling an efficient execution of programs, is introduced. 1. The Parallelism and its Expression Through Data 1.1. A Short Taxonomy of Parallelism Expression in Programming Languages The many existing models and languages for parallel programming lead to an overlap of concepts making the design of a taxonomy a hard task. However, we propose in table 1 a framework used to specify the concepts presented in this paper. Two criteria have been selected to classify the languages: the way they let the programmer express control an...