Checkpointing is a useful technique for rollback recovery of parallel applications. While extensive research has been performed on checkpointing in parallel environments, there are few checkpointers available to application users on commercial parallel computers. This paper presents one such checkpointer: CLIP. CLIP is a user-level library that provides semitransparent checkpointing for parallel programs on the Intel Paragon multicomputer. It is publicly available to Paragon users at no cost. Conceptually, checkpointing a multicomputer is quite straightforward. However, when creating an actual tool for checkpointing a complex machine like the Paragon, many more issues arise that require careful design decisions to be made. Sometimes ease-of-use must be sacrificed for efficiency and/or correctness. This paper details what these decisions are, and how they were made in CLIP. We also present performance data when checkpointing several long-running Paragon applications with CLIP. The bottom line is that a convenient, general-purpose checkpointing tool like CLIP can provide fault-tolerance on a massively parallel multicomputer like the Paragon with very good performance.

In this work we study the issue of performance prediction on the SGI-Power Challenge, a typical representative of the class of shared-memory Symmetric MultiProcessors. On such a platform, the cost of memory accesses varies depending on their locality and on contention among processors. By running a carefully designed suite of microbenchmarks, we provide quantitative evidence that the interaction with the memory hierarchy affects performance far more substantially than other phenomena related to contention. We also fit three cost functions based on variants of the BSP model, which do not account for the hierarchy, and a newly defined function F, expressed in terms of hardware counters, which captures both memory hierarchy and contention effects. We test the accuracy of all the functions on both synthetic and application benchmarks showing that, unlike the other functions, F achieves an excellent level of predictivity in all cases. Although hardware counters are only available at run time, we give evidence that function F can still be employed as a prediction tool by extrapolating values of the counters from pilot runs on small input sizes.

IBM has recently launched an upgrade of the communication subsystem of its SP2 parallel computer. This change affects the communication hardware (high-performance switch and interface adapters) as well as the communication software (MPI implementation). In order to characterize to what extent the execution times of parallel applications will be affected by these changes, a collection of benchmarks has been run on a SP2 with the old communication subsystem and on the same machine after being upgraded. These benchmarks include point to point and collective communication tests as well as complete parallel applications. The performance indicators are the latency and throughput exhibited by the basic communication tests, and the execution time in the case of real applications. Keywords Communication subsystem, message passing networks, massively parallel computers, performance evaluation, IBM SP2. 1 Introduction A long time has passed since the high-performance computing community realized ...

Performance prediction of checkpointing systems in the presence of failures is a well-studied research area. While the literature abounds with performance models of checkpointing systems, none address the issue of selecting runtime parameters other than the optimal checkpointing interval. In particular, the issue of processor allocation is typically ignored. In this paper, we briefly present a performance model for long-running parallel computations that execute with checkpointing enabled. We then discuss how it is relevant to today’s parallel computing environments and software, and present case studies of using the model to select runtime parameters.

Abstract—Considerable work has been done on providing fault tolerance capabilities for different software components on largescale high-end computing systems. Thus far, however, these faulttolerant components have worked insularly and independently and information about faults is rarely shared. Such lack of system-wide fault tolerance is emerging as one of the biggest problems on leadership-class systems. In this paper, we propose a coordinated infrastructure, named CIFTS, that enables system software components to share fault information with each other and adapt to faults in a holistic manner. Central to the CIFTS infrastructure is a Fault Tolerance Backplane (FTB) that enables fault notification and awareness throughout the software stack, includingfault-aware libraries,middleware,andapplications.We present details of the CIFTS infrastructure and the interface specification that has allowed various software programs, including MPICH2, MVAPICH, Open MPI, and PVFS, to plug into the CIFTS infrastructure. Further, through a detailed evaluation we demonstrate the nonintrusive low-overhead capability of CIFTS that letsapplications runwithminimal performance degradation. I.

Many researchers use a home-based lazy release consistent protocol (HLRC) to provide a simple, effective, and scalable way to build software distributed shared memory (DSM) systems. However, the performance of HLRC is notoriously sensitive to the initial page distribution among home nodes. This paper proposes an adaptive HLRC protocol in which the home page designation is able to change according to the observed application sharing pattern. Our system differs from HLRC and other adaptive derivatives in the following respects. First, the number of home nodes for each shared page can be varied, as opposed to having only a single home node. Second, we use prediction in a novel way to dynamically change the the location of home nodes according to different memory access patterns. The home node of each shared page is able to propagate, perish, and migrate. An online home predictor determine whether or not the current node should remain a home node or drop from the current set of home nodes for a given page. Finally, all decisions concerning home node group membership are made locally, eliminating the costly global decision-making communication present in many other systems. Performance evaluations using six well-known DSM benchmarks show that our adaptive protocol outperforms conventional HLRC by up to 60%. 1

We investigate the configuration and performance of remote commodity computing clusters. This is the dynamic pooling of separate clusters into a single large remote cluster via existing LANs or even the Internet. We discuss the configuration and setup of these remote clusters, as well as the networks since these clusters are on separate Ethernet subnets and separate ATM switches. We show that pure switching networks add little additional overhead to remote cluster computing applications, whereas routers can a have significant impact.

Workload characterization is used for modeling and evaluating computing systems at different levels of detail. We present workload characterization for a class of Computational Fluid Dynamics (CFD) applications that solve Partial Differential Equations (PDEs). This workload characterization focuses on three high performance computing platforms: SGI Origin2000, IBM SP-2, and a cluster of Intel Pentium Pro based PCs. We execute extensive measurement-based experiments on these platforms to gather statistics of system resource usage, which lead to a quantitative workload characterization. Our workload characterization approach yields a coarse-grain resource utilization behavior that is being applied for performance modeling and evaluation of distributed high performance metacomputing systems. In addition, this study enhances our understanding of interactions between PDE solver workloads and high performance computing platforms and is useful for tuning applications belonging to this class. 1

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Low latency and high bandwidth networking is essential for cluster computing and System-Area-Networks (SAN). The performance of a SAN optimized interconnect, Myrinet, is compared with gigabit Ethernet running TCP/IP. Though Myrinet has lower latencies and higher throughput than gigabit Ethernet, it is found that an efficient implementation of message passing interface library over TCP/IP achieves performance very close to Myrinet. These observations leads to the fact that gigabit and the upcoming 10 gigabit Ethernet can serve as a cost-effective alternative to specialized interconnects if the efficiency of protocol implementations can be improved. This paper also surveys some recent work being done on increasing the efficiency of TCP/IP and other efficient protocol implementations that benefit all applications using the ubiquitous sockets interface over Ethernet without using specialized libraries such as GM over Myrinet.