A method for finding large isomorphic subgraphs in two similar circuits is proposed, and its application to sequential equivalence checking (SEC) is discussed. SEC ensures correctness of two designs. Among other things, efficient SEC is important for wider adoption of innovative sequential synthesis (SS) methods, which offer substantial reductions in delay, area, power and flip-flop counts, compared to the traditional combinational methods. In practice, some forms of SS, such as clock-gating, modify only a small portion of the design, but because of cyclic dependencies in sequential logic, current SEC solutions have to be applied to the entire designs. This leads to the inability to prove equivalence for important problems. A promising solution to SEC for such situations is to identify large isomorphic subgraphs of the two circuits. Then SEC can be proved by compositional verification. Preliminary experiments show this method can be used effectively for some difficult industrial SEC problems. The method for finding large isomorphic subgraphs is of interest in general and can be used, for example, in incremental physical design. The method is fast and effective. 1

Traditional approaches for sequential logic optimization include (1) explicit state-based techniques such as state minimization, (2) structural techniques such as retiming, and (3) methods that exploit sequential don't-cares derived from unreachable states. These approaches optimize a logic circuit as a single component with a single input/output behavior. In this paper we present a novel concept for sequential optimization referred to as temporal decomposition, which distinguishes the logic that initializes the circuit from the logic needed for the behavior after startup. This work was motivated by a recent observation made for bounded property verification: There is a substantial optimization potential for transition relations when the first execution steps are applied as satisfiability don't-cares. This result suggests that current designs include circuitry that is only used during the first few clock periods after reset and could be discarded or disabled after startup. In this paper we describe how temporal decomposition could be applied to treat the logic for startup separately from the remaining circuitry and discuss multiple alternatives to exploit this for an improved implementation.

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This paper presents a light-weight sweeping method, similar to SAT- and BDD-sweeping. Performance are on the order of 10x to 100x faster than SAT-sweeping for large designs, while achieving about 50-90 % of the reductions. 1

Abstract—Sequential equivalence checking (SEC) technologies, capable of demonstrating the behavioral equivalence of two designs, have grown dramatically in capacity over the past decades. The ability to efficiently identify and leverage internal equivalence points to reduce the domain of the overall SEC problem is central to SEC scalability. However, conditionally equivalent designs – within which internal equivalence may not exist under sequential observability don’t care conditions – are notoriously difficult for automated SEC tools. This paper constitutes one of the first attempts to advance the scalability of SEC for conditionally equivalent designs through automated invariant generation, which enables an inductive solution to an otherwise highlynoninductive problem. Through careful software engineering and various heuristics, this technique has been demonstrated capable of yielding orders of magnitude speedup on difficult industrial conditional SEC problems, in cases constituting the only method that we have found to achieve an automated solution. I.

Abstract — Bounded model checking of partial circuit designs enables the detection of errors even when the implementation of the design is not finished. The behavior of the missing parts can be modeled by a conservative extension of propositional logic, called 01X-logic. Then the transitions of the underlying (incomplete) sequential circuit under verification have to be represented adequately. In this work, we investigate the difference between a relation-oriented and a function-oriented approach for this issue. Experimental results on a large set of examples show that the function-oriented representation is most often superior w. r. t. (1) CPU runtime and (2) accuracy regarding the ability to find a counterexample, such that by using the function-oriented approach an increase of accuracy up to 210% and a speed-up of the CPU runtime up to 390 % compared to the relation-oriented approach are achieved. But there are also relevant examples, e. g. a VLIW-ALU, for which the relationoriented approach outperforms the function-oriented one by 300 % in terms of CPU-time, showing that both approaches are efficient for different scenarios. I.

Abstract — Combinational equivalence checking is an essential task in circuit design. In this paper we focus on SAT based equivalence checking making use of incremental SAT techniques which are well known from their application in Bounded Model Checking. Based on an analysis of shared circuit structures we present heuristics which try to maximize the benefit from incremental SAT solving in this application by looking for good orders in which the equivalence of different circuit outputs is checked. Moreover, we present a reset strategy for situations where the benefit from the incremental SAT approach seems to decrease. Experimental results demonstrate that our novel method outperforms traditional methods significantly. I.