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A High Performance Low Power Filter CMOS Channel
"... Abstract-A new CMOS PCM channel fiiter is described, which includes transmit and receive filters on a single die. This chip displays an idle-channel noise of typically O dBrnCO, a POWeIsupply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW, making it ver ..."
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Abstract-A new CMOS PCM channel fiiter is described, which includes transmit and receive filters on a single die. This chip displays an idle-channel noise of typically O dBrnCO, a POWeIsupply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW, making it very cost effective in telecommunication switching systems. The design of this chip, including architectural, switched capacitor filter, and amplifier considerations is described, and typical experimental results are presented. I.
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"... Reduction of the power dissipation associated with high speed sampling and quantization is a major problem in many applications, including portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers, ..."
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Reduction of the power dissipation associated with high speed sampling and quantization is a major problem in many applications, including portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers,

