FPGA-based synthesis tools require information about behaviour and architectural to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices. 1 Introduction FPGAs offer many advantages for many kinds of applications and present new opportunities for system design [DeHon 94], but their main disadvantages are the limited number of cells available on a single chip and the difficulty of performing global communication. It is important that the available cells are utilized efficiently . One way to do this is to design circuits with a low level schematic editor and manually configure the cells and routing elements. Although this method allows the realization of highly optimised hardware, it has several shortcomings. Design at the gate level is error prone, and c...

We present a method for parametrised partitioning of multidimensional programs for acceleration using a hardware coprocessor. The method involves a divide-andconquer structure, with the "divide" and "merge" phases carried out by a general-purpose processor while the "conquer " phase is handled by application-specific hardware. The partitioning strategy has been captured in a simple functional language, and we have automated the production of partitioned programs in this language. Our approach has been tested on an FPGA-based system using a number of computer vision algorithms,including the Canny edge detector, and the performance is compared against executing the programs on the PC host. 1 Introduction The objective of our research on hardware-software codesign is to develop systems containing both hardware and software components with higher quality, in shorter time, and at lower cost than existing ones. Recent advances in programmable logic, particularly Field-Programmable Gate Arra...

We present an experimental framework for mapping declarative programs, written in a language known as Ruby, into various combinations of hardware and software. Strategies for parametrised partitioning into hardware and software can be captured concisely in this framework, and their validity can be checked using algebraic reasoning. The method has been used to guide the development of prototype compilers capable of producing, from a Ruby expression, a variety of implementations involving fieldprogrammable gate arrays (FPGAs) and microprocessors. The viability of this approach is illustrated using a number of examples for two reconfigurable systems, one containing an array of Algotronix devices and a PC host, and the other containing a transputer and a Xilinx device. 1 Introduction Although it has been known for many years that, from a functional point of view, there is little distinction between hardware and software, in current practice they are mostly developed using very different m...

This paper describes the use of Ruby, a language of functions and relations, to develop serialised implementations of array-based architectures. Our Ruby expressions contain parameters which can be varied to produce a wide range of designs with different space-time trade-offs. Such expressions can be obtained by applying correctness-preserving transformations to an initial simple description. This approach provides a unified treatment of serialisation schemes similar to LPGS (Locally Parallel Globally Sequential) and LSGP (Locally Sequential Globally Parallel) partitioning methods, and will be illustrated by the development of a variety of circuits for convolution. Keywords: Ruby, parametrised design, serialisation, correctness-preserving transformations, systolic arrays. 1 Introduction An attraction of array-based architectures, such as systolic networks, is the opportunity for customising them to cater for a specific application. One way of achieving customisation is to start from ...

We describe a method for speeding up divide-andconquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the "divide" and "merge" phases, while the "conquer" phase is handled by a purpose-built coprocessor. It is shown how transformation techniques from the Ruby language can be adopted in developing a family of systolic sorters, and how one of the resulting designs is prototyped in eight FPGAs on a PC coprocessor board known as CHS2x4 from Algotronix. The execution of the hardware unit is embedded in a sorting program, with the PC host merging the sorted sequences from the hardware sorter. The performance of this implementation is compared against various sorting algorithms on a number of PC systems. 1 Introduction It has long been recognised that the performance of a conventional processor can be speeded up many times if computationally-intensive operations are delegated to purpose-built hardware. Such hardware accele...

. Binomial filters are simple and efficient structures based on the binomial coefficients for implementing Gaussian filtering. They do not require multipliers and can therefore be implemented efficiently in programmable hardware. There are many possible variations of the basic binomial filter structure, and they provide a wide range of space-time trade-offs; a number of these designs have been captured in a parametrised form and their features are compared. This technique can be used for multi-dimensional filtering, provided that the filter is separable. The numerical performance of binomial filters, and their implementation using field-programmable devices for an image processing application, are also discussed. Keywords: Gaussian filters, binomial filters, parametrised design, field-programmable devices. 1. Introduction Gaussian filtering is probably the most common form of linear filtering. To overcome the problem of choosing filter coefficients against a set of conflicting constr...

The declarative language Ruby provides a coherent framework for representing and developing designs. Sketching diagrams for Ruby programs by hand is, however, time-consuming and error-prone. This paper describes a design sketcher which automates the production of a diagram from a Ruby description. 1 INTRODUCTION Text-based languages, such as VHDL, 3 are becoming increasingly popular for developing designs. Their popularity is mainly due to their facilities for parametrising designs, and it is a great bonus if both behaviour and structure can be expressed in a single notation. Moreover, pictorial representations such as circuit schematics can be tedious to create and to modify. Providing visual aid in hardware design is, nevertheless, important. Circuit diagrams, when appropriately drawn, make explicit the basic structure and size of components, allowing designers to obtain rapidly an overview of a design and to locate specific parts on which they can focus. There have been attempts ...

this document which have been, and continue to be, a genuinely inter-disciplinary collaborative venture. In addition, Tony Hoare and Bob McLatchie have been strongly supportive of this work in every way, Bernard Sufrin has provided us with much help on the use of Standard ML, Richard Bird has contributed new algorithms for shared expression extraction, Mark Josephs and Jelio Yantchev have provided useful input on asynchronous models and routing networks. References