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Interconnect Bundle Sizing under Discrete Design Rules
"... Abstract – The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissible interconnect widths and spaces to a small set of discrete values with some interdependencies, so that traditional interconnect sizing by continuousvariable optimization techniques become ..."
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Abstract – The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissible interconnect widths and spaces to a small set of discrete values with some interdependencies, so that traditional interconnect sizing by continuousvariable optimization techniques becomes impossible. We present a dynamic programming (DP) algorithm for simultaneous sizing and spacing of all wires in interconnect bundles, yielding the optimal powerdelay tradeoff curve. DP algorithm sets the width and spacing of all interconnects simultaneously, thus finding the global optimum. The DP algorithm is generic and can handle a variety of powerdelay objectives, such as total power or delay, or weighted sum of both, powerdelay product, max delay and alike. The algorithm consistently yields 6 % dynamic power and 5 % delay reduction for interconnect channels in industrial microprocessor blocks designed in 32 nanometer process technology, when applied as a postlayout optimization step to redistribute wires within interconnect channels of fixed width, without changing the area of the original layout. Index terms – interconnect sizing and spacing, powerdelay optimization, dynamic programming, gridded design rules. I.
On Optimal Ordering of Signals in Parallel Wire Bundles
"... Abstract — Optimal ordering and sizing of wires in a constrainedwidth interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average de ..."
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Abstract — Optimal ordering and sizing of wires in a constrainedwidth interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average delay. Minimizing weighted average delay is a good approximation for MinMax delay optimization. Three variants of monotonic ordering are proven to be optimal, depending on the MCF ratio between the signals at the sides of the bundle and that of the internal wires. The monotonic order property holds for a very broad range of VLSI circuit settings arising in common design practice. A simple, yet nearoptimal, setting of wire widths within the bundle to yield the best average weighted delay is proposed. The theoretical results have been validated by numerical experiments on 65 nanometer process technology and industrial design data. In all cases the ordering optimization yielded improvement in the range of 10 % in wire delay, translated to about 5 % improvement in the clock cycle of a highperformance microprocessor implemented in that technology. Index Terms — routing, wire ordering, wire spacing C I.
TimingAware PowerOptimal Ordering of Signals
"... A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that crosscapacitances between wires are optimally shared. The existence of a unique poweroptimal wire order ..."
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A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that crosscapacitances between wires are optimally shared. The existence of a unique poweroptimal wire order within a bundle is proven, and a method to construct this order is derived. The optimal order of wires depends only on the activity factors of the underlying signals; hence, it can be performed prior to spacing optimization. By using this order of wires, optimality of the combined solution is guaranteed (as compared with any other ordering and spacing of the wires). Timingaware power optimization is enabled by simultaneously considering timing criticality weights and activity factors for the signals. The proposed algorithm has been applied to various interconnect layouts, including wire bundles from highend microprocessor circuits in 65 nm technology. Interconnect power reduction of 17 % on average has been observed in such bundles.
Intel Corporation
"... The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted PowerDelay Sum (WPDS) objective function and derive necessary and sufficient condi ..."
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The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted PowerDelay Sum (WPDS) objective function and derive necessary and sufficient conditions for the existence of optimal interwire space allocation, based on the notion of capacitance density. At the optimum, every wire must be in equilibrium of its linetoline weighted capacitance density on its two opposite sides, and the WPDS of the whole circuit is minimal if and only if capacitance density is uniformly distributed across the entire layout. This condition is shown to be equivalent to all paths of the layout crosscapacitance graph having the same length and all cuts having the same flow. An implementation which has been used in the design of a recent commercial highend microprocessor and yielded 17 % power reduction and 9 % delay reduction in toplevel interconnects is presented.
The Complexity of VLSI PowerDelay Optimization by Interconnect Resizing
"... The lithography used for 32 nanometers and smaller VLSI process technologies restricts the interconnect widths and spaces to a very small set of admissible values. Until recently the sizes of interconnects were allowed to change continuously and the implied powerdelay optimal tradeoff could be formu ..."
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The lithography used for 32 nanometers and smaller VLSI process technologies restricts the interconnect widths and spaces to a very small set of admissible values. Until recently the sizes of interconnects were allowed to change continuously and the implied powerdelay optimal tradeoff could be formulated as a convex programming problem, for which classical search algorithms are applicable. Once the admissible geometries become discrete, continuous search techniques are inappropriate and new combinatorial optimization solutions are in order. A first step towards such solutions is to study the complexity of the problem, which this paper is aiming at. Though dynamic programming has been shown lately to solve the problem, we show that it is NPcomplete. Two typical VLSI design scenarios are considered. The first trades off power and sum of delays ( L 1 and is shown to be NPcomplete by reduction of PARTITION. The second considers power and max delays ( L), and is shown to be NPcomplete by reduction of