Results 1  10
of
33
Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization
 in Proc. Int. Symp. on Physical Design
"... In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal S ..."
Abstract

Cited by 32 (14 self)
 Add to MetaCart
(Show Context)
In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of inductive noise, and shield insertion is needed to minimize inductive noise. We then formulate two simultaneous shield insertion and net ordering (SINO) problems: the optimal SINO/NF problem to find a minarea SINO solution that is free of capacitive and inductive noise, and the optimal SINO/NB problem to find a minarea SINO solution that is free of capacitive noise and is under the given inductive noise bound. We reveal that both optimal SINO problems are NPhard, and propose effective approximate algorithms for the two problems. Experiments show that our SINO/NB algorithm uses from 15% to 57% fewer shield wires when compared to separated net ordering and shield insertion procedure. Furthermore, under practical noise bounds, the SINO/NB solutions use from 44% to 67% fewer shield wires when compared to SINO/NF solutions, and use 10% to 40% fewer shield wires when compared to the theoretical lower bound for optimal SINO/NF solutions. Additionally, all our algorithms are extremely efficient to finish all examples in few seconds. To the best of our knowledge, it is the first work that presents an indepth study on the simultaneous shield insertion and net ordering problem to minimize both capacitive and inductive noise.
Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering
, 2001
"... It has been shown recently that simultaneous shield insertion and net ordering (called SINO/R as only random shields are used) provides an areaefficient solution to reduce the RLC noise. In this paper, we first develop simple formulae with errors less than 10% to estimate the number of shields in t ..."
Abstract

Cited by 22 (2 self)
 Add to MetaCart
It has been shown recently that simultaneous shield insertion and net ordering (called SINO/R as only random shields are used) provides an areaefficient solution to reduce the RLC noise. In this paper, we first develop simple formulae with errors less than 10% to estimate the number of shields in the minarea SINO/R solution. In order to accommodate prerouted P/G wires that also serve as shields, we then formulate two new SINO problems: SINO/SPR and SINO/UPG, and propose effective and efficient twophase algorithms to solve them. Compared to the existing dense wiring fabric scheme, the resulting SINO/SPR and SINO/UPG schemes maintain the regularity of the P/G structure, have negligible penalty on noise and delay variation, and reduce the total routing area by up to 42% and 36%, respectively. Various estimation results developed in this paper can be readily used to guide global routing and highlevel design decisions.
Effects of global interconnect optimizations on performance estimation of deep submicron design
 in Proc. Int. Conf. on Computer Aided Design
, 2000
"... In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we develop a new systemperformance simulation model as a set of studies within the MARCO GSRC ..."
Abstract

Cited by 15 (2 self)
 Add to MetaCart
(Show Context)
In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we develop a new systemperformance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical pointtopoint global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects – and that use of more accurate {1,3} worstcase capacitive coupling noise switch factors substantially increases peak noise estimates compared to traditional {0,2} bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energydelay issues.
A TwistedBundle Layout Structure for Minimizing Inductive Coupling Noise
 Proc. of the IEEE/ACM International Conference on ComputerAided Design
, 2000
"... In this paper, we propose a novel mistedbundle layout structure for minimizing inductive coupling noise. In this structure, we create several routing regions and reorder the routing of nets in each of these routing regions. The purpose is to create complementary and opposite current loops in the t ..."
Abstract

Cited by 13 (0 self)
 Add to MetaCart
(Show Context)
In this paper, we propose a novel mistedbundle layout structure for minimizing inductive coupling noise. In this structure, we create several routing regions and reorder the routing of nets in each of these routing regions. The purpose is to create complementary and opposite current loops in the twistedbundle layout structure, such that the magnetic fluxes arising from any signal net within a misted group cancel each other in the current loop of a net of interest. The effectiveness of the twistedbundle structure in minimizing coupling inductance has been verified by the application of FastHenry extraction on a 16bit bus structure. We achieve about two orders of magnitude reduction in inductive coupling. SPICE simulations also show that the 16bit twistedbundle bus structure is able to maintain high signal integrity at high frequency of operation. 1.
Towards Global Routing With RLC Crosstalk Constraints.
, 2002
"... Conventional global routing minimizes total wire length and congestion. Experiments using large industrial benchmark circuits show that up to 24% of nets in such routing solutions may have RLC crosstalk violations at 3GHz clock. We develop an extremely efficient lengthscaled Keff (LSt 0 model that ..."
Abstract

Cited by 12 (2 self)
 Add to MetaCart
Conventional global routing minimizes total wire length and congestion. Experiments using large industrial benchmark circuits show that up to 24% of nets in such routing solutions may have RLC crosstalk violations at 3GHz clock. We develop an extremely efficient lengthscaled Keff (LSt 0 model that has a high fidelity for longrange RLC crosstalk. We formulate an extended global routing problem (denoted as GSINO) to consider simultaneous shield insertion and net ordering with RLC crosstalk constraints, then propose an effective threephase GSINO algorithm. The GSINO algorithm completely eliminates the RLC crosstalk violations, and has small area and wire length overhead compared to conventional routing.
BuiltIn SelfTest for Signal Integrity
, 2001
"... Unacceptable loss of signal integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test signal integrity in deepsubmicron highspeed interconnects. Various signal integrity problems occurring on such interconnects (e.g. crosstalk, o ..."
Abstract

Cited by 11 (2 self)
 Add to MetaCart
(Show Context)
Unacceptable loss of signal integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test signal integrity in deepsubmicron highspeed interconnects. Various signal integrity problems occurring on such interconnects (e.g. crosstalk, overshoot, noise, skew, etc.) are considered in a unified model. We also present a test methodology that uses a noise detection circuitry to detect low integrity signals and an inexpensive test architecture to measure and read the statistics for final observation and analysis.
Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint
, 2001
"... For multiple coupled RLC nets, we formulate the minarea simultaneous shield insertion and net ordering (SINO/NB v) problem to satisfy the given noise bound. We develop an e#cient and conservative model to compute the peak noise, and apply the noise model to a simulatedannealing (SA) based algorit ..."
Abstract

Cited by 10 (1 self)
 Add to MetaCart
For multiple coupled RLC nets, we formulate the minarea simultaneous shield insertion and net ordering (SINO/NB v) problem to satisfy the given noise bound. We develop an e#cient and conservative model to compute the peak noise, and apply the noise model to a simulatedannealing (SA) based algorithm for the SINO/NBv problem. Extensive and accurate experiments show that the SAbased algorithm is e#cient, and always achieves solutions satisfying the given noise bound. It uses up to 71% and 30% fewer shields when compared to a greedy based shield insertion algorithm and a separated shield insertion and net ordering algorithm, respectively. To the best of our knowledge, it is the first work that presents an indepth study on the minarea SINO problem under an explicit noise constraint.
Clocktree RLC extraction with efficient inductance modeling
 In Proc. Design Automation and Test in Europe
, 2000
"... Abstract. In this paper, we present an efficient yet accurate inductance extraction methodology and its application to clocktree RLC extraction. We first show that without loss of accuracy, the extraction problem of n traces with or without ground planes can be reduced to a number of onetrace and t ..."
Abstract

Cited by 9 (4 self)
 Add to MetaCart
(Show Context)
Abstract. In this paper, we present an efficient yet accurate inductance extraction methodology and its application to clocktree RLC extraction. We first show that without loss of accuracy, the extraction problem of n traces with or without ground planes can be reduced to a number of onetrace and twotrace subproblems. We then solve onetrace and twotrace subproblems via a tablebased approach. In particular, this method combined with linear cascading assumption have been applied successfully to the clocktree RLC extraction and optimization. I.
Modeling the Effects of Systematic Process Variation on Circuit Performance
 in PhD thesis, EECS, MIT
, 2001
"... As technology scales, understanding semiconductor manufacturing variation becomes essential to effectively design high performance circuits. Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise. Conventional circuit techniques t ..."
Abstract

Cited by 8 (0 self)
 Add to MetaCart
(Show Context)
As technology scales, understanding semiconductor manufacturing variation becomes essential to effectively design high performance circuits. Knowledge of process variation is important to optimize critical path delay, minimize clock skew, and reduce crosstalk noise. Conventional circuit techniques typically represent the interconnect and device parameter variations as random variables. However, recent studies have shown that strong spatial pattern dependencies exist, especially when considering interconnect variation in chemical mechanical polishing (CMP) processes. Therefore, the total variation can be separated into systematic and random components, where a significant portion of the variation can be modeled based on layout characteristics. Modeling the systematic components of different variation sources and implementing these effects in circuit simulation are key to reduce design uncertainty and maximize circuit performance. This thesis presents a methodology to incorporate systematic pattern dependent interconnect
Fullchip Routing Optimization with RLC Crosstalk Budgeting
, 2002
"... Existing layout optimization methods for RLC crosstalk reduction assume a set of interconnects with a priori given crosstalk bounds in a routing region. RLC crosstalk budgeting is critical for effectively applying these methods at the fullchip level. In this paper, we formulate a fullchip routing ..."
Abstract

Cited by 8 (3 self)
 Add to MetaCart
(Show Context)
Existing layout optimization methods for RLC crosstalk reduction assume a set of interconnects with a priori given crosstalk bounds in a routing region. RLC crosstalk budgeting is critical for effectively applying these methods at the fullchip level. In this paper, we formulate a fullchip routing optimization problem with RLC crosstalk budgeting, and solve this problem with a multiphase algorithm. In phase I, we solve an optimal RLC crosstalk budgeting based on linear programming to partition crosstalk bounds at sinks into bounds for net segments in routing regions. In phase II, we perform simultaneous shield insertion and net ordering to meet the partitioned crosstalk bounds in each region. In phase III, we carry out a local refinement procedure to reduce the total number of shields. Compared to the best alternative approach in experiments, the proposed algorithm reduces the total routing area by up to 5.71 % and uses less runtime. To the best of our knowledge, this work is the first indepth study on fullchip routing optimization with RLC crosstalk budgeting.