In recent years, reduced-order modeling techniques based on Krylov-subspace iterations, especially the Lanczos algorithm and the Arnoldi process, have become popular tools to tackle the large-scale time-invariant linear dynamical systems that arise in the simulation of electronic circuits. This paper reviews the main ideas of reduced-order modeling techniques based on Krylov subspaces and describes the use of reduced-order modeling in circuit simulation. 1 Introduction Krylov-subspace methods, most notably the Lanczos algorithm [81, 82] and the Arnoldi process [5], have long been recognized as powerful tools for large-scale matrix computations. Matrices that occur in large-scale computations usually have some special structures that allow to compute matrix-vector products with such a matrix (or its transpose) much more efficiently than for a dense, unstructured matrix. The most common structure is sparsity, i.e., only few of the matrix entries are nonzero. Computing a matrix-vector pr...

Means of applying Krylov subspace techniques for adaptively extracting accurate reducedorder models of large-scale nonlinear dynamical systems is a relatively open problem. There has been much current interest in developing such techniques. We focus on a bi-linearization method, which extends Krylov subspace techniques for linear systems. In this approach, the nonlinear system is first approximated by a bilinear system through Carleman bilinearization. Then a reduced-order bilinear system is constructed in such a way that it matches certain number of multimoments corresponding to the first few kernels of the Volterra-Wiener representation of the bilinear system. It is shown that the two-sided Krylov subspace technique matches significant more number of multimoments than the corresponding one-side technique.

In this paper we develop a gate level model that allows us to determine the best and worst case delay when there is dominant interconnect coupling. Assuming that the gate input windows of transition are known, the model can predict the worst and best case noise, as well as the worst and best case impact on delay. This is done in terms of a Ceff based gate model under general RC interconnect loading conditions. I. INTRODUCTION As IC dimensions scale to the deep submicron range, their multi-level interconnects are constructed such that the coupling capacitance becomes the dominant component of load capacitance. This effect is largely the result of the increased ratio between the lateral and the vertical capacitance of the line. The increased number of metal layers is the other source of coupling capacitance problems, since there is a reduced likelihood of a nearby "ground plan." The lateral capacitance is increased by the relative increase in the metal thickness with respect to line sp...

This paper discusses the analysis of large linear electrical networks consisting of passive components, such as resistors, capacitors, inductors, and trans-formers. Such networks admit a symmetric formula-tion of their circuit equations. We introduce SyPVL, an eficient and numerically stable algorithm for the computation of reduced-order models of large, linear, passive networks. SyPVL represents the specializa-tion of the more general PVL algorithm, to symmetric problems. Besides the gain in eficiency over PVL, SyPVL also preserves the symmetry of the problem, and, as a consequence, can often guarantee the sta-bility of the resulting reduced-order models. Moreover, these reduced-order models can be synthesized as actual physical circuits, thus facilitating compatibility with existing analysis tools. The application of SyPVL is illustrated with two interconnect-analysis examples. 1

The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach has been shown to be overly pessimistic in some cases, while somewhat optimistic in others. This paper introduces TACO, a timing analysis methodology that produces tight bounds on worst- and best-case timing for circuits with dominant coupling capacitance. The methodology utilizes a coupled Ceff gate model for capturing the provably worst- and bestcase delays as a function of the timing-window inputs to the gates.

We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15 % of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. For the small tree topology considered, we observe improvements of at least 18 % in the accuracy of delay estimates when compared to the Elmore model (which isindependent of inductance), even though our estimates are as easy to compute as Elmore delay. The speedup of delay estimation via our analytical model is several orders of magnitude when compared to a simulation methodology such as SPICE. 1.

Three algorithms for the model reduction of large-scale, continuous-time, time-invariant, linear, dynamical systems with a sparse or structured transition matrix and a small number of inputs and outputs are described. They rely on low rank approximations to the controllability and observability Gramians, which can eciently be computed by ADI based iterative low rank methods. The rst two model reduction methods are closely related to the well-known square root method and Schur method, which are balanced truncation techniques. The third method is a heuristic, balancing-free technique. The performance of the model reduction algorithms is studied in numerical experiments.

This paper reviews the main ideas of reduced-order modeling techniques based on Krylov subspaces and describes some applications of reduced-order modeling in circuit simulation

In this paper we review the state of affairs in the area of approximation of large-scale systems. We distinguish among three basic categories, namely the SVD-based, the Krylov-based and the SVD-Krylov-based approximation methods. The first two were developed independently of each other and have distinct sets of attributes and drawbacks. The third approach seeks to combine the best attributes of the first two. Contents 1 Introduction and problem statement 1 2 Motivating Examples 3 3 Approximation methods 4 3.1 SVD-based approximation methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.1 The Singular value decomposition: SVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.2 Proper Orthogonal Decomposition (POD) methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.3 Approximation by balanced truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic stages with large complex coupled interconnects. In timing analysis, the worst-case delay of gates along a critical path must include the effect of noise due to switching of nearby aggressor gates. In this paper, we propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align aggressor inputs to determine the worst-case victim delay. We demonstrate the application of our methodology at both the transistor-level and celllevel. In addition, we prove that the waveforms generated in our methodology converge under typical timing analysis conditions. 1.