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271
Clocking Design and Analysis for a 600MHz Alpha Microprocessor
, 1998
"... Design, analysis, and verification of the clock hierarchy on a 600MHz Alpha microprocessor is presented. The clock hierarchy includes a gridded global clock, gridded major clocks, and many local clocks and local conditional clocks, which together improve performance and power at the cost of verific ..."
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Cited by 50 (1 self)
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Design, analysis, and verification of the clock hierarchy on a 600MHz Alpha microprocessor is presented. The clock hierarchy includes a gridded global clock, gridded major clocks, and many local clocks and local conditional clocks, which together improve performance and power at the cost of verification complexity. Performance is increased with a windowpane arrangement of global clock drivers for lowering skew and employing local clocks for time borrowing. Power is reduced by using major clocks and local conditional clocks. Complexity is managed by partitioning the analysis depending on the type of clock. Design and characterization of global and major clocks use both an AWEsimbased computeraided design (CAD) tool and SPICE. Design verification of local clocks relies on SPICE along with a timingbased methodology CAD tool that includes datadependent coupling, datadependent gate loads, and resistance effects.
Krylov Subspace Techniques for ReducedOrder Modeling of Nonlinear Dynamical Systems
 Appl. Numer. Math
, 2002
"... Means of applying Krylov subspace techniques for adaptively extracting accurate reducedorder models of largescale nonlinear dynamical systems is a relatively open problem. There has been much current interest in developing such techniques. We focus on a bilinearization method, which extends Kry ..."
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Cited by 50 (3 self)
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Means of applying Krylov subspace techniques for adaptively extracting accurate reducedorder models of largescale nonlinear dynamical systems is a relatively open problem. There has been much current interest in developing such techniques. We focus on a bilinearization method, which extends Krylov subspace techniques for linear systems. In this approach, the nonlinear system is first approximated by a bilinear system through Carleman bilinearization. Then a reducedorder bilinear system is constructed in such a way that it matches certain number of multimoments corresponding to the first few kernels of the VolterraWiener representation of the bilinear system. It is shown that the twosided Krylov subspace technique matches significant more number of multimoments than the corresponding oneside technique.
Calculating WorstCase Gate Delays Due to Dominant Capacitance Coupling
, 1997
"... In this paper we develop a gate level model that allows us to determine the best and worst case delay when there is dominant interconnect coupling. Assuming that the gate input windows of transition are known, the model can predict the worst and best case noise, as well as the worst and best case im ..."
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Cited by 47 (2 self)
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In this paper we develop a gate level model that allows us to determine the best and worst case delay when there is dominant interconnect coupling. Assuming that the gate input windows of transition are known, the model can predict the worst and best case noise, as well as the worst and best case impact on delay. This is done in terms of a Ceff based gate model under general RC interconnect loading conditions. I. INTRODUCTION As IC dimensions scale to the deep submicron range, their multilevel interconnects are constructed such that the coupling capacitance becomes the dominant component of load capacitance. This effect is largely the result of the increased ratio between the lateral and the vertical capacitance of the line. The increased number of metal layers is the other source of coupling capacitance problems, since there is a reduced likelihood of a nearby "ground plan." The lateral capacitance is increased by the relative increase in the metal thickness with respect to line sp...
Algorithms for Model Reduction of Large Dynamical Systems
, 1999
"... Three algorithms for the model reduction of largescale, continuoustime, timeinvariant, linear, dynamical systems with a sparse or structured transition matrix and a small number of inputs and outputs are described. They rely on low rank approximations to the controllability and observability Gram ..."
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Cited by 43 (1 self)
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Three algorithms for the model reduction of largescale, continuoustime, timeinvariant, linear, dynamical systems with a sparse or structured transition matrix and a small number of inputs and outputs are described. They rely on low rank approximations to the controllability and observability Gramians, which can eciently be computed by ADI based iterative low rank methods. The rst two model reduction methods are closely related to the wellknown square root method and Schur method, which are balanced truncation techniques. The third method is a heuristic, balancingfree technique. The performance of the model reduction algorithms is studied in numerical experiments.
KrylovSubspace Methods for ReducedOrder Modeling in Circuit Simulation
 J. Comput. Appl. Math
, 1999
"... The simulation of electronic circuits involves the numerical solution of very largescale, sparse, in general nonlinear, systems of differentialalgebraic equations. Often, the size of these systems can be reduced considerably by replacing the equations corresponding to linear subcircuits by approxim ..."
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Cited by 43 (9 self)
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The simulation of electronic circuits involves the numerical solution of very largescale, sparse, in general nonlinear, systems of differentialalgebraic equations. Often, the size of these systems can be reduced considerably by replacing the equations corresponding to linear subcircuits by approximate models of much smaller statespace dimension. In this paper, we describe the use of Krylovsubspace methods for generating such reducedorder models of linear subcircuits. Particular emphasis is on reducedorder modeling techniques that preserve the passivity of linear RLC subcircuits. Key words: Lanczos algorithm; Arnoldi process; Linear dynamical system; VLSI interconnect; Transfer function; Pad'e approximation; Stability; Passivity; Positive real function 1 Introduction Today's integrated electronic circuits are extremely complex, with up to tens of millions of devices. Prototyping of such circuits is no longer possible, and instead, computational methods are used to simulate and ...
Approximation of largescale dynamical systems: An overview
, 2001
"... In this paper we review the state of affairs in the area of approximation of largescale systems. We distinguish among three basic categories, namely the SVDbased, the Krylovbased and the SVDKrylovbased approximation methods. The first two were developed independently of each other and have dist ..."
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Cited by 43 (2 self)
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In this paper we review the state of affairs in the area of approximation of largescale systems. We distinguish among three basic categories, namely the SVDbased, the Krylovbased and the SVDKrylovbased approximation methods. The first two were developed independently of each other and have distinct sets of attributes and drawbacks. The third approach seeks to combine the best attributes of the first two. Contents 1 Introduction and problem statement 1 2 Motivating Examples 3 3 Approximation methods 4 3.1 SVDbased approximation methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.1 The Singular value decomposition: SVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.2 Proper Orthogonal Decomposition (POD) methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.3 Approximation by balanced truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
ReducedOrder modeling of large passive linear circuits by means of the SyPVL algorithm
 in Tech. Dig. 1996 IEEE/ACM International Conference on ComputerAided Design
, 1996
"... This paper discusses the analysis of large linear electrical networks consisting of passive components, such as resistors, capacitors, inductors, and transformers. Such networks admit a symmetric formulation of their circuit equations. We introduce SyPVL, an eficient and numerically stable algorit ..."
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Cited by 42 (14 self)
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This paper discusses the analysis of large linear electrical networks consisting of passive components, such as resistors, capacitors, inductors, and transformers. Such networks admit a symmetric formulation of their circuit equations. We introduce SyPVL, an eficient and numerically stable algorithm for the computation of reducedorder models of large, linear, passive networks. SyPVL represents the specialization of the more general PVL algorithm, to symmetric problems. Besides the gain in eficiency over PVL, SyPVL also preserves the symmetry of the problem, and, as a consequence, can often guarantee the stability of the resulting reducedorder models. Moreover, these reducedorder models can be synthesized as actual physical circuits, thus facilitating compatibility with existing analysis tools. The application of SyPVL is illustrated with two interconnectanalysis examples. 1
TACO: Timing Analysis With COupling
 in Proc. of the Design Automation Conf
, 2000
"... The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach has been shown to be overly pessimistic in some cases, while somewhat optimistic in others. This paper introduces TACO, a ..."
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Cited by 39 (1 self)
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The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach has been shown to be overly pessimistic in some cases, while somewhat optimistic in others. This paper introduces TACO, a timing analysis methodology that produces tight bounds on worst and bestcase timing for circuits with dominant coupling capacitance. The methodology utilizes a coupled Ceff gate model for capturing the provably worst and bestcase delays as a function of the timingwindow inputs to the gates.
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
 the IEEE Transactions on CAD. (Available
"... The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are ..."
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Cited by 38 (0 self)
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The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a pessimistic estimate, and the restriction to step response delay estimation. In this paper, we prove that the Elmore delay is an absolute upper bound on the 50 % delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore delay metric as we use it for design automation. I.
An analytical delay model for RLC interconnects
 IEEE Trans. Comput.Aided Des
, 1997
"... We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15 % of SPICEcomputed delay across a wide range of interconnect parameter values. We also ex ..."
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Cited by 37 (4 self)
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We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15 % of SPICEcomputed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of sourcesink delays in arbitrary interconnect trees. For the small tree topology considered, we observe improvements of at least 18 % in the accuracy of delay estimates when compared to the Elmore model (which isindependent of inductance), even though our estimates are as easy to compute as Elmore delay. The speedup of delay estimation via our analytical model is several orders of magnitude when compared to a simulation methodology such as SPICE. 1.