In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.

As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.

Abstract—An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100 % fault detection coverage and the optimal interconnect diagnosis resolution. Index Terms—Crosstalk fault, delay fault, fault diagnosis, interconnections, oscillation ring (OR) test scheme. I.

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As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-on-chips is becoming dominant. More specifically, distortion (integrity loss) of signals traveling on high-speed interconnects can no longer be ignored. In this paper, we propose a new fault model, called multiple transition, and its corresponding test pattern generation mechanism. We also extend the conventional boundaryscan architecture to allow testing signal integrity in SoC interconnects. Our extended JTAG architecture collects and outputs the integrity loss information using the enhanced observation cells. The architecture fully complies with the JTAG standard and can be adopted by any SoC that is IEEE 1149.1 compliant.

We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use the power profile of non-embedded cores to find the best mix of their test pattern subsets that satisfy the power and/or time constraints. An MILP formulation is presented to globally perform the power-time tradeoff and produce the SoC test schedule. Many constraints including peak/average power of cores, time/sequencing requirements, and ATE pin limitation are also incorporated within this formulation. I.

In this paper the influence of crosstalk on single victim due to multiple aggressors in the same metal layer is studied. We develop here a crosstalk fault model based on the consideration of usual distributed coupling capacitance and RLGC parasitics of interconnects in addition to mutual conductance (resistive bridging) in order to deal the crosstalk influence. Here, we estimate the crosstalk influence for worst case input signal combinations on aggressors, which induce more crosstalk on single victim. Our model helps the System-on-Chip (SoC) designers by providing sufficient insights into Signal Integrity problems. Experimental simulations with our crosstalk model, carried out using Philips CMOS12 (130nm) technology parameters, further validated with PSPICE simulations reveal that coupling capacitance’s effect is more on crosstalk glitch and signal delay on victim’s output whereas, the mutual conductance affects more on the final steady state value of the victim’s output signal. KEY WORDS Worst case crosstalk, multiple aggressors, single victim, glitch-delay-final steady state value, ABCD model 1.

The paper proposes an ABCD modeling approach to model the crosstalk coupling noise on the victim interconnect due to single / multiple aggressor(s) in deep sub-micron (DSM) chips. After the order reduction the crosstalk model is utilized for the analysis of crosstalk coupling noise on the victim’s far end signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure in prior the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling noise introduces the delay in the victim‘s far end signal which can be significant enough or even unacceptable if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to manufacturing defect such as under-etching or even, length of the victim interconnect is increased due to improper layouts of / routings between cores and devices on chips. Influences of other interconnect parasitics on the victim´s far end signal can also be analyzed using the same model. Simulation results obtained with the proposed reduced order model is found to be quite comparable to the accuracy of the PSPICE simulation. 1.

The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-ona-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC’02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.