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193
Phase Noise in Oscillators: a Unifying Theory and Numerical Methods for Characterization
 IEEE Transactions on Circuits and Systems
, 2000
"... Abstract—Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields, such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques f ..."
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Cited by 117 (11 self)
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Abstract—Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields, such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterization. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterization of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on a variety of practical electrical oscillators and obtain good matches with measurements, even at frequencies close to the carrier, where previous techniques break down. Our methods are more than three orders of magnitude faster than the bruteforce Monte Carlo approach, which is the only previously available technique that can predict phase noise correctly. Index Terms—Circuit simulation, FokkerPlanck equations, nonlinear oscillators, oscillator noise, phase noise, stochastic
Precise Delay Generation Using Coupled Oscillators
 IEEE J. SolidState Circuits
, 1994
"... This thesis describes a new class of delay generation structures which can produce precise delays with subgate delay resolution. These structures are based on coupled ring oscillators which oscillate at the same frequency. One such structure, called an array oscillator, consists of a linear array o ..."
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Cited by 54 (19 self)
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This thesis describes a new class of delay generation structures which can produce precise delays with subgate delay resolution. These structures are based on coupled ring oscillators which oscillate at the same frequency. One such structure, called an array oscillator, consists of a linear array of ring oscillators. A unique coupling arrangement forces the outputs of the ring oscillators to be uniformly offset in phase by a precise fraction of a buffer delay. This arrangement enables the array oscillator to achieve a delay resolution equal to a buffer delay divided by the number of rings. Another structure, called a delay line oscillator, consists of a series of delay stages, each based on a single coupled ring oscillator. These delay stages uniformly span the delay interval to which they are phase locked. Each delay stage is capable of generating a phase shift that varies over a positive and negative range. These characteristics allow the structure to precisely subdivide delays into arbitrarily small intervals.
Optimal design of a CMOS opamp via geometric programming
 IEEE Transactions on ComputerAided Design
, 2001
"... We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er ..."
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Cited by 51 (10 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal tradeo s among competing performance measures such aspower, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeo curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a
Jitter in Ring Oscillators
 IEEE Journal of SolidState Circuits
, 1997
"... work in this thesis would not have been possible without many people whose contributions are now acknowledged. At Analog Devices Semiconductor: Larry DeVito, Rosamaria Croughwell, and Alex Gusinov, engineers with whom it was a genuine pleasure to work; Bob Surette, for outstanding support in laborat ..."
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Cited by 49 (1 self)
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work in this thesis would not have been possible without many people whose contributions are now acknowledged. At Analog Devices Semiconductor: Larry DeVito, Rosamaria Croughwell, and Alex Gusinov, engineers with whom it was a genuine pleasure to work; Bob Surette, for outstanding support in laboratory measurements; Tony Freitas, for considerable layout expertise; Dennis Buss, for allimportant financial support; Maryanne Masterson and Frank Holden for fabrication and trim support; Bob Adams, Paul Brokaw, Barrie Gilbert, Janos Kovacs, and Chris Mangelsdorf for enlightening conversations. At Tektronix: Scott Casstevens, for providing the CSA803A for high accuracy jitter measurements; Laszlo Dobos, for his insights into jitter. At Boston University: Anton Mavretic, for his direction and support; David Perreault, Mark Horenstein, and Emile Gergin for their time and effort on the
A 1.9GHz wideband IF double conversion CMOS receiver for cordless telephone applications
 IEEE Journal of SolidState Circuits
, 1997
"... Rapid growth in the portable communications market has pushed designers to seek lowcost, lowpower, highly integrated solutions for the RF transceiver. A number of recent efforts have concentrated on integrating many of the discrete radio receiver components in a lowcost silicon process such as CM ..."
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Cited by 39 (1 self)
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Rapid growth in the portable communications market has pushed designers to seek lowcost, lowpower, highly integrated solutions for the RF transceiver. A number of recent efforts have concentrated on integrating many of the discrete radio receiver components in a lowcost silicon process such as CMOS [1][2]. This paper describes a prototype of a monolithic CMOS receiver that combines RF and baseband functionality by taking the carrier signal at the LNA input and producing a 10bit digital baseband waveform. A WideBand Intermediate Frequency Double Conversion (WBIFDC) architecture is utilized to remove the need for external narrowband IF filters.
Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits
 IEEE Trans. CAD
, 1999
"... As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology base ..."
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Cited by 27 (5 self)
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noisestability metric is introduced to demonstrate how noise can be analyzed systematically on a fullchip basis using simulationbased transistorlevel analysis. We then describe Harmony, a twolevel (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reducedorder modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be use...
A Mathematical Basis For PowerReduction In Digital VLSI Systems
 IEEE Trans. Circuits Syst. II
, 1997
"... Presented in this paper is a mathematical basis for powerreduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing powerreduction techniques under a common framework. The proposed basis is derived from informatio ..."
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Cited by 24 (15 self)
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Presented in this paper is a mathematical basis for powerreduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing powerreduction techniques under a common framework. The proposed basis is derived from informationtheoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Architectures implementing a given algorithm are equivalent to communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. By including various implementation constraints, increasingly realistic lower bounds are calculated. The usefulness of the proposed theory is demonstrated via...
White Noise in MOS Transistors and Resistors
 IEEE Circuits and Devices
, 1993
"... Shot noise and thermal noise have long been considered the results of two distinct mechanisms, but they aren't. ..."
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Cited by 22 (0 self)
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Shot noise and thermal noise have long been considered the results of two distinct mechanisms, but they aren't.
Predicting the Phase Noise and Jitter of PLLBased Frequency Synthesizers. www.designersguide.com
, 2003
"... Version 4g, August 2006 Two methodologies are presented for predicting the phase noise and jitter of a PLLbased frequency synthesizer using simulation that are both accurate and efficient. The methodologies begin by characterizing the noise behavior of the blocks that make up the PLL using transisto ..."
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Cited by 21 (2 self)
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Version 4g, August 2006 Two methodologies are presented for predicting the phase noise and jitter of a PLLbased frequency synthesizer using simulation that are both accurate and efficient. The methodologies begin by characterizing the noise behavior of the blocks that make up the PLL using transistorlevel RF simulation. For each block, the phase noise or jitter is extracted and applied to a model for the entire PLL.
Continuoustime feedback in floatinggate MOS circuits
 IEEE Trans. Circuits Syst
, 2001
"... Abstract—We present the negative and positivefeedback circuit configurations of continuoustime floatinggate MOS circuits. We start by reviewing the dynamics of our pFET and nFET singletransistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circui ..."
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Cited by 17 (6 self)
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Abstract—We present the negative and positivefeedback circuit configurations of continuoustime floatinggate MOS circuits. We start by reviewing the dynamics of our pFET and nFET singletransistor synapses. We present the range of possible stabilizing and destabilizing types of feedback in circuits with one floatinggate synapse, including data from nFET and pFET synapses. We then show examples of competitive and cooperative behavior in multiplesynapse circuits. We present experimental data from circuits fabricated in the 2 m nwell CMOS process available through MOSIS. We see similar experimental effects in 1.2 and 0.5 m processes. Index Terms—Continuous floatinggate programming, electron tunneling, floatinggate circuits, floatinggate dynamics, hotelectron injection. I.