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434
Phase Noise in Oscillators: a Unifying Theory and Numerical Methods for Characterization
 IEEE Transactions on Circuits and Systems
, 2000
"... Abstract—Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields, such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques f ..."
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Cited by 180 (22 self)
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Abstract—Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields, such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterization. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterization of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on a variety of practical electrical oscillators and obtain good matches with measurements, even at frequencies close to the carrier, where previous techniques break down. Our methods are more than three orders of magnitude faster than the bruteforce Monte Carlo approach, which is the only previously available technique that can predict phase noise correctly. Index Terms—Circuit simulation, FokkerPlanck equations, nonlinear oscillators, oscillator noise, phase noise, stochastic
Noise in deep submicron digital design
 in Proc. of the International Conference on ComputerAided Design (ICCAD
, 1996
"... As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper denes noise as it pertains to digital systems and addresses the technology trends which are bringing n ..."
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Cited by 76 (6 self)
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper denes noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is dened, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with onchip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise. 1
Optimal design of a CMOS opamp via geometric programming
 IEEE Transactions on ComputerAided Design
, 2001
"... We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er ..."
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Cited by 75 (10 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal tradeo s among competing performance measures such aspower, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeo curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a
Precise delay generation using coupled oscillators
 IEEE Journal of SolidState Circuits
, 1993
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Jitter in ring oscillators
 IEEE Journal of SolidState Circuits
, 1997
"... Abstract — Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phaselocked loop (PLL). A major contribution is the identification of a design figure of me ..."
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Cited by 64 (1 self)
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Abstract — Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phaselocked loop (PLL). A major contribution is the identification of a design figure of merit , which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuitlevel noise sources (such as thermal and shot noise) to systemlevel jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clockrecovery PLL’s which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closedloop jitter is within 10 % of the design procedure prediction. Index Terms—Design methodology, jitter, noise measurement, oscillator noise, oscillator stability, phase jitter, phaselocked loops, phase noise, voltage controlled oscillators. I.
A 1.9GHz wideband IF double conversion CMOS receiver for cordless telephone applications
 IEEE Journal of SolidState Circuits
, 1997
"... Rapid growth in the portable communications market has pushed designers to seek lowcost, lowpower, highly integrated solutions for the RF transceiver. A number of recent efforts have concentrated on integrating many of the discrete radio receiver components in a lowcost silicon process such as CM ..."
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Cited by 46 (1 self)
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Rapid growth in the portable communications market has pushed designers to seek lowcost, lowpower, highly integrated solutions for the RF transceiver. A number of recent efforts have concentrated on integrating many of the discrete radio receiver components in a lowcost silicon process such as CMOS [1][2]. This paper describes a prototype of a monolithic CMOS receiver that combines RF and baseband functionality by taking the carrier signal at the LNA input and producing a 10bit digital baseband waveform. A WideBand Intermediate Frequency Double Conversion (WBIFDC) architecture is utilized to remove the need for external narrowband IF filters.
Predicting the Phase Noise and Jitter of PLLBased Frequency Synthesizers. www.designersguide.com
, 2003
"... Version 4g, August 2006 Two methodologies are presented for predicting the phase noise and jitter of a PLLbased frequency synthesizer using simulation that are both accurate and efficient. The methodologies begin by characterizing the noise behavior of the blocks that make up the PLL using transisto ..."
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Cited by 36 (2 self)
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Version 4g, August 2006 Two methodologies are presented for predicting the phase noise and jitter of a PLLbased frequency synthesizer using simulation that are both accurate and efficient. The methodologies begin by characterizing the noise behavior of the blocks that make up the PLL using transistorlevel RF simulation. For each block, the phase noise or jitter is extracted and applied to a model for the entire PLL.
Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits
 IEEE Trans. CAD
, 1999
"... As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology base ..."
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Cited by 30 (5 self)
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noisestability metric is introduced to demonstrate how noise can be analyzed systematically on a fullchip basis using simulationbased transistorlevel analysis. We then describe Harmony, a twolevel (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reducedorder modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be use...
White Noise in MOS Transistors and Resistors
 IEEE Circuits and Devices
, 1993
"... Shot noise and thermal noise have long been considered the results of two distinct mechanisms, but they aren't. ..."
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Cited by 28 (1 self)
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Shot noise and thermal noise have long been considered the results of two distinct mechanisms, but they aren't.
A mathematical basis for powerreduction in digital VLSI systems
 IEEE Trans. CAS Part II
, 1997
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