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Digital Circuit Optimization via Geometric Programming
 Operations Research
, 2005
"... informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently s ..."
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Cited by 38 (7 self)
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informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistorcapacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.
CouplingDriven Signal Encoding Scheme for LowPower Interface Design
, 2000
"... Coupling effects between onchip interconnects must be addressed in ultra deep submicron VLSI and systemonachip (SoC) designs. A new lowpower bus encoding scheme is proposed to minimize coupled switchings which dominate the onchip bus power consumption. The couplingdriven bus invert method use ..."
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Cited by 34 (3 self)
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Coupling effects between onchip interconnects must be addressed in ultra deep submicron VLSI and systemonachip (SoC) designs. A new lowpower bus encoding scheme is proposed to minimize coupled switchings which dominate the onchip bus power consumption. The couplingdriven bus invert method use slim encoder and decoder architecture to minimize the hardware overhead. Experimental results indicate that our encoding methods save effective switchings as much as 30% in an 8bit bus with onecycle redundancy. 1 Introduction Increased coupling effect between interconnects in ultra deep submicron technology not only aggravates the powerdelay metrics but also deteriorates the signal integrity due to capacitive and inductive crosstalk noises. Conventional approaches to interconnect synthesis aim at optimal interconnect structures in terms of interconnect topology, wire width and spacing, and buffer location and sizes [3]. In this paper, we study a signal encoding scheme to minimize coupli...
Test Pattern Generation for Signal Integrity Faults on Long Interconnects
 in Proc. VLSI Test Symp. (VTS’02
, 2002
"... In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction met ..."
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Cited by 13 (2 self)
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In this paper, we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.
BuiltIn SelfTest for Signal Integrity
, 2001
"... Unacceptable loss of signal integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test signal integrity in deepsubmicron highspeed interconnects. Various signal integrity problems occurring on such interconnects (e.g. crosstalk, o ..."
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Cited by 11 (2 self)
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Unacceptable loss of signal integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test signal integrity in deepsubmicron highspeed interconnects. Various signal integrity problems occurring on such interconnects (e.g. crosstalk, overshoot, noise, skew, etc.) are considered in a unified model. We also present a test methodology that uses a noise detection circuitry to detect low integrity signals and an inexpensive test architecture to measure and read the statistics for final observation and analysis.
Signal Integrity: Fault Modeling and Testing in HighSpeed SoCs
, 2002
"... As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz systemonchips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliab ..."
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Cited by 7 (0 self)
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As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz systemonchips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the highspeed interconnects. Then, we present a BISTbased test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz systemonchips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.
An Efficient Method for LargeScale Gate Sizing
 IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications
"... Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimumallowed gate size. This problem is well known to be a geometric program (GP), and can be solved by ..."
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Cited by 6 (1 self)
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Abstract—We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimumallowed gate size. This problem is well known to be a geometric program (GP), and can be solved by using standard interiorpoint methods for small and mediumsize problems with up to several thousand gates. In this paper, we describe a new method for solving this problem that handles far larger circuits, up to a million gates, and is far faster. Numerical experiments show that our method can compute an adequately accurate solution within around 200 iterations; each iteration, in turn, consists of a few passes over the circuit. In particular, the complexity of our method, with a fixed number of iterations, is linear in the number of gates. A simple implementation of our algorithm can size a 10 000 gate circuit in 25 s, a 100 000 gate circuit in 4 min, and a million gate circuit in 40 min, approximately. For the million gate circuit, the associated GP has three million variables and more than six million monomial terms in its constraints; as far as we know, these are the largest GPs ever solved. Index Terms—Gate sizing, geometric programming (GP), largescale optimization. I.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 1 An Efficient Method for Largescale Gate Sizing
"... Abstract — We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimum allowed gate size. This problem is well known to be a geometric program (GP), and can be solved ..."
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Abstract — We consider the problem of choosing the gate sizes or scale factors in a combinational logic circuit in order to minimize the total area, subject to simple RC timing constraints, and a minimum allowed gate size. This problem is well known to be a geometric program (GP), and can be solved using standard interiorpoint methods for small and medium size problems with up to several thousand gates. In this paper we describe a new method for solving this problem that handles far larger circuits, up to a million gates, and is far faster. Numerical experiments show that our method can compute an adequately accurate solution within around 200 iterations; each iteration, in turn, consists of a few passes over the circuit. In particular, the complexity of our method, with a fixed number of iterations, is linear in the number of gates. A simple implementation of our algorithm can size a 10000 gate circuit in 25 seconds, a 100000 gate circuit in 4 minutes, and a million gate circuit in 40 minutes, approximately. For the million gate circuit, the associated GP has 3 million variables and more than 6 million monomial terms in its constraints; as far as we know, these are the largest GPs ever solved. Index Terms — Gate sizing, geometric programming, largescale optimization.