We first consider online speed scaling algorithms to minimize the energy used subject to the constraint that every job finishes by its deadline. We assume that the power required to run at speed ¡ is ¢¤ £. We provide a tight bound on the competitive ratio of the previously pro-posed Optimal Available algorithm. This improves the best known competitive ratio by a factor � � of. We then introduce a new online algorithm, and show that this algorithm’s competitive ratio is at � £ �� � £ �¨����¥�¥����� � most. This competitive ratio is significantly better and is � ������� approximately for large �. Our result is essentially tight for large �. In particular, as � approaches infinity, we show that any algorithm must have competitive ratio �� � (up to lower order terms). We then turn to the problem of dynamic speed scaling to minimize the maximum temperature that the device ever reaches, again subject to the constraint that all jobs finish by their deadlines. We assume that the device cools according to Fourier’s law. We show how to solve this problem in polynomial time, within any error bound, using the Ellipsoid algorithm. 1.

This paper contributes a comprehensive study of a framework to bound worst-case instruction cache performance for caches with arbitrary levels of associativity. The framework is formally introduced, operationally described and its correctness is shown. Results of incorporating instruction cache predictions within pipeline simulation show that timing predictions for set-associative caches remain just as tight as predictions for direct-mapped caches. The low cache simulation overhead allows interactive use of the analysis tool and scales well with increasing associativity. The approach taken is based on a data-ow specication of the problem and provides another step toward worst-case execution time prediction of contemporary architectures and its use in schedulability analysis for hard real-time systems.

We survey recent research that has appeared in the theoretical computer science literature on algorithmic

System level synthesis is widely seen as the solution for closing the productivity gap in system design. High level system models are used in system level design for early design exploration. While real time operating systems (RTOS) are an increasingly important component in system design, specific RTOS implementations can not be used directly in high level models. On the other hand, existing system level design languages (SLDL) lack support for RTOS modeling. In this paper we propose a RTOS model built on top of existing SLDLs which, by providing the key features typically available in any RTOS, allows the designer to model the dynamic behavior of multi-tasking systems at higher abstraction levels to be incorporated into existing design flows. Experimental result shows that our RTOS model is easy to use and efficient while being able to provide accurate results.

The paper describes modeling and performance control of an Internet server using classical feedback control theory. We show that classical feedback control can leverage on well-known real-time scheduling results to resolve one of the fundamental problems in Internetservers today; namely, achieving overload protection and performance guarantees in the presence of load unpredictability. The research is motivated by the increasing proliferation of a new category of Web-based services, such as online trading, banking, and business transactions, where performance guarantees are required in the face of unpredictable server load. Failure to meet desired performance levels may result in loss of customers, financial damage or liability violations. State-of-the-art Web servers are not designed to offer such performance guarantees. We show that control theory offers a robust solution to the server performance control problem. We demonstrate that a general web server may be modeled as a linear ti...

Cache prediction for preemptive scheduling is an open issue despite its practical importance. First analysis approaches use simplified models for cache behavior or they assume simplified preemption and execution scenarios that seriously impact analysis precision. We present an analysis approach which considers multiple executions of processes and preemption scenarios for static priority periodic scheduling. The results of our experiments show that caches introduce a strong and complex timing dependency between process executions that are not appropriately captured in the simplified models.

Determining safe and tight upper bounds on the worst-case execution time (WCET) of hard real-time tasks running on contemporary microarchitectures is a difficult problem. Current trends in microarchitecture design have created a complexity wall: By enhancing performance through ever more complex architectural features, systems have become increasingly hard to analyze. This paper extends a framework, introduced previously as Virtual Simple Architecture (VISA), to multi-tasking real-time systems. The objective of VISA is to obviate the need to statically analyze complex processors by instead shifting the burden of guaranteeing deadlines – in part – onto the hardware. The VISA framework exploits a complex processor that ordinarily operates with all of its advanced features enabled, called the complex mode, but which can also be downgraded to a simple mode by gating off the advanced

The contributions of this paper are threefold. First, a solution to the problem of prioritized mutual exclusion in a distributed system is proved correct. This protocol is based on fewer requirements than prioritized extensions of other protocols and outperforms other protocols with an average complexity of (log n) and a worst-case complexity of O(n) messages for n nodes. Second, the concept of relative fairness is introduced, which quantifies the relation between parallel events in terms of their ordering in the absence of synchronized clocks. This concept is applied to the protocol in order to determine a requirement to guarantee a certain order between events when message delays are bounded. Third, the protocol is extended to prevent priority inversion by incorporating the priority inheritance and the priority ceiling protocols. The extensions are shown to integrate well with the original protocol. They impose the same message overhead as mentioned before for each dynamically raise...

Fast and accurate estimation is critical for exploration of any design space in general. As we move to higher levels of abstraction, estimation of complete system designs at each level of abstraction is needed. Estimation should provide a variety of useful metrics relevant to design tasks in different domains and at each stage in the design process. In this paper, we present such a system-level estimation approach based on a novel combination of dynamic profiling and static retargeting. Co-estimation of complete system implementations is fast while accurately reflecting even dynamic effects. Furthermore, retargetable profiling is supported at multiple levels of abstraction, providing multiple design quality metrics at each level. Experimental results show the applicability of the approach for efficient design space exploration.

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