Unacceptable loss of signal integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test signal integrity in deep-submicron high-speed interconnects. Various signal integrity problems occurring on such interconnects (e.g. crosstalk, overshoot, noise, skew, etc.) are considered in a unified model. We also present a test methodology that uses a noise detection circuitry to detect low integrity signals and an inexpensive test architecture to measure and read the statistics for final observation and analysis.

As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.

The rising level of complexity and speed of SoC makes it increasingly vital to test adequately the system for signal integrity. Voltage overshoot is one of the integrity factors that has not been sufficiently addressed for the purpose of testing and reliability. Overshoots are known to inject hot-carriers into the gate oxide and cause permanent degradation of MOSFET transistors' performance. This performance degradation creates a serious reliability concern. Unfortunately, accurate parasitic extraction and simulation to detect the interconnect problems is very time consuming and very sensitive to the circuit characteristics and thus is not practical for large SoC.

Embedded system implementations must be flexible, power-efficient and the non-recurring engineering (NRE) cost must be low. To deal with those conflicting requirements a platform-based approach is advocated. Three platform generations are identified. The first generation targets programmable video applications. Computational performance is the challenge and designs are optimized for timing. To control the NRE cost Intellectual Property (IP) blocks are reused as much as possible. In the second generation the bottleneck shifts from computation to communication. Networks on a chip are introduced including layered services. Since the target application domain shifts to mobile applications designs are now optimized for power dissipation. In the third generation systems become smarter, more adaptive and show a lot of interaction with the environment. New Deep Sub-micron problems like variability and soft errors make that designs are now optimized for yield. The layered network-based approach is well suited to solve these problems also. In the foreseeable future it is expected that the scaling towards smaller dimensions as predicted by Moore’s law will continue. The ITRS roadmap [1] will not suddenly come to an end in the near future.

The paper proposes an ABCD modeling approach to model the crosstalk coupling noise on the victim interconnect due to single / multiple aggressor(s) in deep sub-micron (DSM) chips. After the order reduction the crosstalk model is utilized for the analysis of crosstalk coupling noise on the victim’s far end signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure in prior the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling noise introduces the delay in the victim‘s far end signal which can be significant enough or even unacceptable if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to manufacturing defect such as under-etching or even, length of the victim interconnect is increased due to improper layouts of / routings between cores and devices on chips. Influences of other interconnect parasitics on the victim´s far end signal can also be analyzed using the same model. Simulation results obtained with the proposed reduced order model is found to be quite comparable to the accuracy of the PSPICE simulation. 1.