Unacceptable loss of signal integrity may harm the functionality of SoCs permanently or intermittently. We propose a systematic approach to model and test signal integrity in deep-submicron high-speed interconnects. Various signal integrity problems occurring on such interconnects (e.g. crosstalk, overshoot, noise, skew, etc.) are considered in a unified model. We also present a test methodology that uses a noise detection circuitry to detect low integrity signals and an inexpensive test architecture to measure and read the statistics for final observation and analysis.

As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.

Abstract – A new methodology is proposed to improve the tolerance of synchronous digital circuits to powersupply voltage (VDD) and temperature (T) variations, without degrading its performance. The goal is to avoid yield loss, due to unmet time specifications in high-performance products. The purpose of this paper is to discuss design trade-offs of the basic mixed-signal building block – a Dynamic Delay Buffer (DDB). In the proposed methodology, we dynamically control the instant of data capture (the clock edge trigger) in key memory cells, according to local VDD and/or T variations, to avoid loss of data integrity. A delay model is used to design the DDB block, according to the time slack and process variations, in order to optimize the gains in circuit tolerance to VDD and/or T variations. Experimental results based on SPICE simulations (including Monte Carlo simulations) for ITC’99 benchmark sequential circuits are used to demonstrate that careful design may lead to 40 % improvements on circuit tolerance to VDD and/or T variations. Index Terms: signal integrity; power-supply transients; temperature variations; dynamic clock driving; tolerant design. 1.

As IC technology scales down, interconnect issues are becoming one of the major concerns of gigahertz System-on-Chip (SoC) design. Voltage distortion (power supply noise) and delay violations (signal and clock skews) dramatically contribute to signal integrity loss. As a consequence, performance degradation, reliability problems and ultimately, functional error occur. In this paper, we propose a new methodology to enhance SoC signal integrity with respect to power/ground voltage transients, without degrading its performance. The underlying principle of the proposed methodology is to dynamically adapt the clock duty-cycle (CDC) according to the signal propagation delay through the logic whose power supply voltage is being disturbed.

Abstract – A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of powersupply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. In the proposed methodology, we dynamically control the instant of data capture (the clock edge trigger) in key memory cells, according to local VDD and/or T variations. This way, data integrity lost is avoided, and circuit tolerance to power supply and/or temperature variations is enhanced. The methodology is based on a Dynamic Delay Buffer (DDB) block, used to sense VDD/T variations and to induce dynamic clock skews driving a limited subset of memory elements. Experimental results based on SPICE

As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-on-chips is becoming dominant. More specifically, distortion (integrity loss) of signals traveling on high-speed interconnects can no longer be ignored. In this paper, we propose a new fault model, called multiple transition, and its corresponding test pattern generation mechanism. We also extend the conventional boundaryscan architecture to allow testing signal integrity in SoC interconnects. Our extended JTAG architecture collects and outputs the integrity loss information using the enhanced observation cells. The architecture fully complies with the JTAG standard and can be adopted by any SoC that is IEEE 1149.1 compliant.