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Goaloriented requirements analysis and reasoning in the tropos methodology
 Engineering Applications of Artificial Intelligence
, 2005
"... Abstract. Tropos is an agentoriented software methodology proposed in [1, 2]. The methodology is founded on the notions of agent and goal, and goal analysis is used extensively to support software development during different phases. This paper adopts a formal goal model defined and analyzed in [9, ..."
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Cited by 18 (7 self)
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Abstract. Tropos is an agentoriented software methodology proposed in [1, 2]. The methodology is founded on the notions of agent and goal, and goal analysis is used extensively to support software development during different phases. This paper adopts a formal goal model defined and analyzed in [9, 15] to make the goal analysis process concrete through the use of forward and backward reasoning for goal models. The formal goal analysis is illustrated through examples, using an implemented goal reasoning tool.
QB or not QB: An efficient execution verification tool for memory orderings
 In ComputerAided Verification (CAV), LNCS 3114
, 2004
"... Abstract. We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models—an important step during postsilicon verification of multiprocessor machines. We employ our previously reported style of writing formal specifications for shared memory mod ..."
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Cited by 17 (2 self)
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Abstract. We study the problem of formally verifying shared memory multiprocessor executions against memory consistency models—an important step during postsilicon verification of multiprocessor machines. We employ our previously reported style of writing formal specifications for shared memory models in higher order logic (HOL), obtaining intuitive as well as modular specifications. Our specification consists of a conjunction of rules that constrain the global visibility order. Given an execution to be checked, our algorithm generates Boolean constraints that capture the conditions under which the execution is legal under the visibility order. We initially took the approach of specializing the memory model HOL axioms into equivalent (for the execution to be checked) quantified boolean formulae (QBF). As this technique proved inefficient, we took the alternative approach of converting the HOL axioms into a program that generates a SAT instance when run on an execution. In effect, the quantifications in our memory model specification were realized as iterations in the program. The generated Boolean constraints are satisfiable if and only if the given execution is legal under the memory model. We evaluate two different approaches to encode the Boolean constraints, and also incremental techniques to generate and solve Boolean constraints. Key results include a demonstration that we can handle executions of realistic lengths for the modern Intel Itanium memory model. Further research into proper selection of Boolean encodings, incremental SAT checking, efficient handling of transitivity, and the generation of unsatisfiable cores for locating errors are expected to make our technique practical. 1
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
, 2004
"... The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementin ..."
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Cited by 17 (7 self)
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The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementing each output signal of the circuit. This is usually done using reachability graphs.
A hybrid BDD and SAT finite domain constraint solver
 IN: PROCEEDINGS OF PADL.
, 2006
"... Finitedomain constraint solvers based on Binary Decision Diagrams (BDDs) are a powerful technique for solving constraint problems over finite set and integer variables represented as Boolean formulæ. Boolean Satisfiability (SAT) solvers are another form of constraint solver that operate on constrai ..."
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Cited by 15 (6 self)
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Finitedomain constraint solvers based on Binary Decision Diagrams (BDDs) are a powerful technique for solving constraint problems over finite set and integer variables represented as Boolean formulæ. Boolean Satisfiability (SAT) solvers are another form of constraint solver that operate on constraints on Boolean variables expressed in clausal form. Modern SAT solvers have highly optimized propagation mechanisms and also incorporate efficient conflictclause learning algorithms and effective search heuristics based on variable activity, but these techniques have not been widely used in finitedomain solvers. In this paper we show how to construct a hybrid BDD and SAT solver which inherits the advantages of both solvers simultaneously. The hybrid solver makes use of an efficient algorithm for capturing the inferences of a finitedomain constraint solver in clausal form, allowing us to automatically and transparently construct a SAT model of a finitedomain constraint problem. Finally, we present experimental results demonstrating that the hybrid solver can outperform both SAT and finitedomain solvers by a substantial margin.
Detecting State Coding Conflicts in STG Unfoldings Using SAT
 IN PROC. OF THE 4TH INT. CONF. ON APPLICATION OF CONCURRENCY TO SYSTEM DESIGN
"... The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is that of identifying whether an STG satisfies t ..."
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Cited by 13 (9 self)
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The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is that of identifying whether an STG satisfies the Complete State Coding (CSC) requirement, e.g., by using model checking based on the state graph of an STG. In
Optimizations for compiling declarative models into Boolean formulas
 In 8th International Conference on Theory and Applications of Satisfiability Testing (SAT 2005), St.Andrews
, 2005
"... Abstract. Advances in SAT solver technology have enabled many automated analysis and reasoning tools to reduce their input problem to a SAT problem, and then to use an efficient SAT solver to solve the underlying analysis or reasoning problem. The solving time for SAT solvers can vary substantially ..."
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Cited by 12 (3 self)
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Abstract. Advances in SAT solver technology have enabled many automated analysis and reasoning tools to reduce their input problem to a SAT problem, and then to use an efficient SAT solver to solve the underlying analysis or reasoning problem. The solving time for SAT solvers can vary substantially for semantically identical SAT problems depending on how the problem is expressed. This property motivates the development of new optimization techniques whose goal is to produce more efficiently solvable SAT problems, thereby improving the overall performance of the analysis or reasoning tool. This paper presents our experience using several mechanical techniques that enable the Alloy Analyzer to generate optimized SAT formulas from firstorder logic formulas. These techniques are inspired by similar techniques from the field of optimizing compilers, suggesting the potential presence of underlying connections between optimization problems from two very different domains. Our experimental results show that our techniques can deliver substantial performance improvement results—in some cases, they reduce the solving time by an order of magnitude. 1
Nogood recording from restarts
 In Proceedings of the 20th International Joint Conference on Artificial Intelligence (IJCAI’2007
, 2007
"... In this paper, nogood recording is investigated within the randomization and restart framework. Our goal is to avoid the same situations to occur from one run to the next one. More precisely, nogoods are recorded when the current cutoff value is reached, i.e. before restarting the search algorithm. ..."
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Cited by 12 (2 self)
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In this paper, nogood recording is investigated within the randomization and restart framework. Our goal is to avoid the same situations to occur from one run to the next one. More precisely, nogoods are recorded when the current cutoff value is reached, i.e. before restarting the search algorithm. Such a set of nogoods is extracted from the last branch of the current search tree. Interestingly, the number of nogoods recorded before each new run is bounded by the length of the last branch of the search tree. As a consequence, the total number of recorded nogoods is polynomial in the number of restarts. Experiments over a wide range of CSP instances demonstrate the effectiveness of our approach. 1
Accelerating highlevel bounded model checking
 In Proceedings of the 2006 IEEE/ACM international conference on Computeraided design, ICCAD ’06
, 2006
"... {malay  agupta} at neclabs dot com ..."
ConSUS: a lightweight program conditioner
 Journal of Systems and Software
, 2005
"... Program conditioning consists of identifying and removing a set of statements which cannot be executed when a condition of interest holds at some point in a program. It has been applied to problems in maintenance, testing, re–use and re–engineering. Program conditioning relies upon both symbolic exe ..."
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Cited by 10 (3 self)
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Program conditioning consists of identifying and removing a set of statements which cannot be executed when a condition of interest holds at some point in a program. It has been applied to problems in maintenance, testing, re–use and re–engineering. Program conditioning relies upon both symbolic execution and reasoning about symbolic predicates. Automation of the process therefore requires some form of automated theorem proving. However, the use of a fullpower ‘heavyweight ’ theorem prover would impose unrealistic performance constraints. This paper reports on a lightweight approach to theorem proving using the FermaT simplify decision procedure. This is used as a component to ConSUS, a program conditioning system for the Wide Spectrum Language WSL. The paper describes the symbolic execution algorithm used by ConSUS, which prunes as it conditions. The paper also provides empirical evidence that conditioning produces a significant reduction in program size and, although exponential in the worst case, the conditioning system has low degree polynomial behaviour in many cases, thereby making it scalable to unit level applications of program conditioning.
A SATbased Sudoku solver
 12 th International Conference on Logic for Programming, Artificial Intelligence and Reasoning, LPAR 2005
, 2005
"... Abstract. This paper presents a SATbased Sudoku solver. A Sudoku is translated into a propositional formula that is satisfiable if and only if the Sudoku has a solution. A standard SAT solver can then be applied, and a solution for the Sudoku can be read off from the satisfying assignment returned ..."
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Cited by 9 (1 self)
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Abstract. This paper presents a SATbased Sudoku solver. A Sudoku is translated into a propositional formula that is satisfiable if and only if the Sudoku has a solution. A standard SAT solver can then be applied, and a solution for the Sudoku can be read off from the satisfying assignment returned by the SAT solver. No coding was necessary to implement this solver: The translation into propositional logic is provided by a framework for finite model generation available in the Isabelle/HOL theorem prover. Only the constraints on a Sudoku solution had to be specified in the prover’s logic. 1