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This paper presents a formal technique for system-level power/performance analysis that can help the designer to select the right platform starting from a set of target applications. By platform we mean a family of heterogeneous architectures that satisfy a set of architectural constraints imposed to allow re-use of hardware and software components. More precisely, we introduce the Stochastic Automata Networks (SANs) as an effective formalism for average-case analysis that can be used early in the design cycle to identify the best power/performance figure among several application-architecture combinations. This information not only helps avoid lengthy profiling simulations, but also enables efficient mappings of the applications onto the chosen platform. We illustrate the features of our technique through the design of an MPEG-2 video decoder application.

We present a comprehensive experimental study of ten leading algorithms for the minimum mean cycle problem. For most of these algorithms, there has not been a clear understanding of their performance in practice although theoretical bounds have been proved for their running times. Only an experimental study can shed light on whether changes in an algorithm that make its running time theoretically more efficient are worth the overhead in terms of their payoff in practice. To this end, our experimental study provides a great deal of insight. In our evaluation, we programmed these algorithms uniformly and efficiently. We systematically compared them on a test suite composed of random graphs as well as benchmark circuits. Above all, our experimental results provide important insights into the individual performance as well as relative performance of these algorithms in practice. One of the most surprising results of this study is that Howard's algorithm, a well known algorithm to the stoch...

An embedded system #the system# continuously interacts with its environment under strict timing constraints, called the external constraints, and it is important to knowhow these external constraints translate to time budgets, called the internal constraints, on the tasks of the system. Knowing these time budgets reduces the complexity of the system 's design and validation problem and helps the designers have a simultaneous control on the system's functional as well as temporal correctness from the beginning of the design #ow. The translation is carried out by #rst deriving the rate of each task in the system, hence the term #rate derivation", using the system's task structure and the rates of the input stimuli coming into the system from its environment. The derived task rates are later used to derive and validate the rest of the internal as well as external constraints. This paper proposes a general task graph model to represent the system's task structure, techniques for deriving ...

The objective of this paper is to introduce the Stochastic Automata Networks (SANs) as an effective formalism for application modeling in system-level analysis. More precisely, we present a methodology for application modeling for system-level power/performance analysis that can help the designer to select the right platform and implement a set of target multimedia applications. We also show that, under various input traces, the steady-state behavior of the application itself is characterized by very different ‘clusterings’ of the probability distributions. Having this information available, not only helps to avoid lengthy profiling simulations for predicting power and performance figures, but also enables efficient mappings of the applications onto a chosen platform. We illustrate the benefits of our methodology using the MPEG-2 video decoder as the driver application.

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The increasingly complex design of embedded systems creates the problems of specifying consistent and satisfiable rate constraints on process execution rates,checking them for consistency and satisfiability, computing process execution rates, and debugging rate constraint violations. The high complexity of these problems requires a complete and automated framework to help the designer in producing correct systems in shorter design time. We present such a framework and its implementation in a tool called Ratan. Experiments on large benchmarks show the suitability of the tool for an interactive debugging environment.

Abstract—This paper formally models and studies latencyinsensitive systems (LISs) through max-plus algebra. We introduce state traces to model behaviors of LISs and obtain a formally proved performance upper bound achievable by latencyinsensitive design. An implementation of the latency-insensitive protocol that can provide robust communication through backpressure is also proposed. The intrinsic performance of the proposed implementation is acquired based on state traces. It is also proved that the proposed implementation can always reach the best performance achievable by latency-insensitive design. Index Terms—Back-pressure, latency-insensitive system, maxplus algebra, performance analysis, state trace.

The design of embedded (reactive and real-time) systems has become increasingly difficult due to increasing design complexity and shortening time to market. This also worsens the design validation of the system. One remedy is to move to higher levels of abstraction for validation and to trickle down the validation results at higher levels to lower levels of abstraction in the design cycle. In this paper, we propose a methodology for timingdriven high-level embedded system design and validation. This methodology combines analysis, simulation, and interaction throughout the design cycle. It is interaction with designers that we think is what makes this methodology most effective. The proposed tool for this methodology will provide system designers a larger design space to explore and allow them to observe and control the timing effects across the entire design process. 1 Introduction The design of embedded (reactive and real-time) systems has become increasingly difficult due to the f...

We address the problem of timing constraint derivation and validation for reactive and real-time embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the system first to derive the timing constraints on the system's internal behavior and then use them to derive and validate the timing constraints on the system's external behavior. Our solution consists of the following contributions: (1) a generalized task graph model and a comprehensive classification of timing constraints, (2) algorithms for derivation and validation of timing constraints of the system modeled in the generalized task graph model, (3) new and improved algorithms for finding the performance of cyclic embedded systems and a comprehensive comparison of the existing algorithms, (4) a general formulation of the problem of debugging timing violations in cyclic embedded systems and it...