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Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions
 In IEEE/ACM International Conference on ComputerAided Design (ICCAD
, 2008
"... Abstract — The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*trees. The practically relevant solution space ..."
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Abstract — The analog placement algorithm Plantage, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*trees. The practically relevant solution space is thereby enumerated quasicomplete. The sets of possible placements of the basic building blocks are represented and combined in a new efficient way, using enhanced shape functions. The result of Plantage is the Pareto front of placements with respect to different aspect ratios. The whole approach is deterministic, in contrast to existing analog placement algorithms. I.
Analog Layout Synthesis Recent Advances in Topological Approaches
"... Abstract—This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layoutaware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constrai ..."
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Abstract—This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layoutaware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequencepairs, B*trees, circuit hierarchy and layout templates are described as advantageous means to tackle these tasks. I.
Analog Placement Based on SymmetryIsland Formulation
"... Abstract—To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity ..."
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Abstract—To reduce the effect of parasitic mismatches and circuit sensitivity to thermal gradients or process variations for analog circuits, some pairs of modules need to be placed symmetrically with respect to a common axis, and the symmetric modules are preferred to be placed at closest proximity for better electrical properties. Most previous works handle the problem with symmetry constraints by imposing symmetricfeasible conditions in floorplan representations and using cost functions to minimize the distance between symmetric modules. Such approaches are inefficient due to the large search space and cannot guarantee the closest proximity of symmetry modules. In this paper, we present the first lineartimepacking algorithm for the placement with symmetry constraints using the topological floorplan representations. We first introduce the concept of a symmetry island which is formed by modules of the same symmetry group in a single connected placement. Based on this concept and the B ∗tree representation, we propose automatically symmetricfeasible (ASF) B ∗trees to directly model the placement of a symmetry island. We then present hierarchical B ∗trees (HB ∗trees) which can simultaneously optimize the placement with both symmetry islands and nonsymmetric modules. Unlike the previous works, our approach can place the symmetry modules in a symmetry group in close proximity and significantly reduce the search space based on the symmetryisland formulation. In particular, the packing time for an ASFB ∗tree or an HB ∗tree is the same as that for a plain B ∗tree (only linear) and much faster than previous works. Experimental results show that our approach achieves the bestpublished quality and runtime efficiency for analog placement. Index Terms—Analog circuit, floorplanning, physical design, placement. I.
Plantage A Deterministic Analog Placement Approach
"... www.eda.ei.tum.de This demonstration gives an overview of our deterministic analog placement approach Plantage [9]. Guided by the hierarchical structure of an analog circuit, Plantage generates a set of placements. 1 ..."
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www.eda.ei.tum.de This demonstration gives an overview of our deterministic analog placement approach Plantage [9]. Guided by the hierarchical structure of an analog circuit, Plantage generates a set of placements. 1