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**21 - 28**of**28**### EFFICIENT COMPUTATION OF THE AREAPOWER CONSUMPTION VERSUS DELAY TRADEOFF CURVE FOR CIRCUIT CRITICAL PATH OPTIMIZATION

"... The paper introduces a novel methodology to obtain the entire arealpower consumption versus delay tradeoff curve for the crit-ical path of a combinational logic circuit in a very efficient way. Compared to other proposed ways based on the optimization of the whole circuit for every point of the trad ..."

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The paper introduces a novel methodology to obtain the entire arealpower consumption versus delay tradeoff curve for the crit-ical path of a combinational logic circuit in a very efficient way. Compared to other proposed ways based on the optimization of the whole circuit for every point of the tradeoff curve, in this work only a subset of the boolean network representing the circuit is optimized each time. Performance comparison and results based on the MCNC'91 set of two-level benchmark circuits are given. It is demonstrated that the proposed methodology produces trade-off curves for large circuits of thousands of gates greatly reducing the computation complexity (measured in number of variables of an equivalent linear programming problem) by a factor up to 16 times. 1.

### Optimisation of Full-Custom Logic Cells Using Response Surface Methodology

, 2000

"... Introduction: The design of digital circuits, especially for full-custom cells, is often a time consuming and laborious process relying on the intuition and heuristic knowledge of the designer. Optimising transistor sizes is the main key in meeting the various design specifications such as time-dela ..."

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Introduction: The design of digital circuits, especially for full-custom cells, is often a time consuming and laborious process relying on the intuition and heuristic knowledge of the designer. Optimising transistor sizes is the main key in meeting the various design specifications such as time-delay, area and power. The problem with this type of design optimisation is the large number of design variables leading to an explosion in the design space. Various solutions to these problems have been proposed which are based on the use of either static timing models [1], dynamic timing models [2] or a combination of the two [3]. Static timing models, while efficient in computation, do not take all transition states into account, resulting in low accuracy. Dynamic timing models, on the other hand, require the consideration of all possible input combinations and therefore suffer from the dimensionality problem. We propose to use a set of techniques known as design of experiments (DOE)

### Power Optimization of Delay Constrained Circuits

- Computer Science Department, University of California, Los Angeles
, 1986

"... We present a framework for combining Voltage Scaling and Gate sizing techniques for power optimizations. Our results show that the combination of the two techniques perform better than the techniques applied in isolation. We introduce a new heuristic for choosing gates for sizing and voltage scali ..."

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We present a framework for combining Voltage Scaling and Gate sizing techniques for power optimizations. Our results show that the combination of the two techniques perform better than the techniques applied in isolation. We introduce a new heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the loading capacitance of the gates. Our results show an average power reduction of 73 % when decisions are taken assuming dynamic power only and an average power reduction of 77 % when decisons include the short circuit power dissipation. The circuit under consideration are delay contrained and first optimized for delay under the environment of SIS. 1 Introduction Advances in se...

### ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems

, 2006

"... Convex optimization problems are very popular in the VLSI design society due to their guaranteed convergence to a global optimal point. Table data is often fitted into analytical forms like posynomials to make them convex. However, fitting the look-up tables into posynomial forms with minimum error ..."

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Convex optimization problems are very popular in the VLSI design society due to their guaranteed convergence to a global optimal point. Table data is often fitted into analytical forms like posynomials to make them convex. However, fitting the look-up tables into posynomial forms with minimum error itself may not be a convex optimization problem and hence excessive fitting errors may be introduced. In recent literature numerically convex tables have been proposed. These tables are created optimally by minimizing the perturbation of data to make them numerically convex. But since these tables are numerical, it is extremely important to make the table data smooth, and yet preserve its convexity. Smoothness will ensure that the convex optimizer behaves in a predictable way and converges quickly to the global optimal point. In this paper, we propose to simultaneously create optimal numerically convex look-up tables and guarantee smoothness in the data. We show that numerically ”convexifying ” and ”smoothing ” the table data with minimum perturbation can be formulated as a convex semidefinite optimization problem and hence optimality can be reached in polynomial time. We present our convexifying and smoothing results on industrial cell libraries. ConvexSmooth shows 14X reduction in fitting error over a well-developed posynomial fitting algorithm.

### Gaze Sizing and Buffer Insertion Algorithm . . .

"... In this paper, we propose an efficient algorithm to reduce glitch power dissipation in CMOS logic circuits. The proposed algorithm takes path balancing approach that is achieved by gate sizing and buffer insertion methods. The gate sizing technique reduces not only glitches, but also effective capac ..."

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In this paper, we propose an efficient algorithm to reduce glitch power dissipation in CMOS logic circuits. The proposed algorithm takes path balancing approach that is achieved by gate sizing and buffer insertion methods. The gate sizing technique reduces not only glitches, but also effective capacitance in the circuit. After gate sizing, buffer insertion is performed for those remaining unbalanced paths that are not covered by gate sizing. Buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the power consumed by the inserted buffers. The ILP (Integer Linear Program) has been employed to determine the location of inserted buffers, which is a very difficult problem because the power reduction by buffer insertion is closely related to other inserted buffers. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show that 61.5 % of glitch reduction and 30.4 % of power reduction are achieved without increasing the critical path delay.

### Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology

"... Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree ..."

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Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interior-point methods for semidefinite programming. The method is applied to two important sizing problems- sizing of clock meshes, and sizing of buses in the presence of crosstalk. 1

### unknown title

"... SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design ..."

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SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design