Abstract not found

Convex optimization problems are very popular in the VLSI design society due to their guaranteed convergence to a global optimal point. Table data is often fitted into analytical forms like posynomials to make them convex. However, fitting the look-up tables into posynomial forms with minimum error itself may not be a convex optimization problem and hence excessive fitting errors may be introduced. In recent literature numerically convex tables have been proposed. These tables are created optimally by minimizing the perturbation of data to make them numerically convex. But since these tables are numerical, it is extremely important to make the table data smooth, and yet preserve its convexity. Smoothness will ensure that the convex optimizer behaves in a predictable way and converges quickly to the global optimal point. In this paper, we propose to simultaneously create optimal numerically convex look-up tables and guarantee smoothness in the data. We show that numerically ”convexifying ” and ”smoothing ” the table data with minimum perturbation can be formulated as a convex semidefinite optimization problem and hence optimality can be reached in polynomial time. We present our convexifying and smoothing results on industrial cell libraries. ConvexSmooth shows 14X reduction in fitting error over a well-developed posynomial fitting algorithm.

In this paper, we propose an efficient algorithm to reduce glitch power dissipation in CMOS logic circuits. The proposed algorithm takes path balancing approach that is achieved by gate sizing and buffer insertion methods. The gate sizing technique reduces not only glitches, but also effective capacitance in the circuit. After gate sizing, buffer insertion is performed for those remaining unbalanced paths that are not covered by gate sizing. Buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the power consumed by the inserted buffers. The ILP (Integer Linear Program) has been employed to determine the location of inserted buffers, which is a very difficult problem because the power reduction by buffer insertion is closely related to other inserted buffers. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show that 61.5 % of glitch reduction and 30.4 % of power reduction are achieved without increasing the critical path delay.

Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to highperformance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interior-point methods for semidefinite programming. The method is applied to two important sizing problems- sizing of clock meshes, and sizing of buses in the presence of crosstalk. 1

SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design