Abstract{A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized by an inertial delay and separate delays between its inputs and output. The technology constraint, related tofeasible ranges of lengths and widths of transistors, is speci ed bya parameter u b.Itistheupper bound on the di erence between the input to output delays corresponding to any pair of inputs of a gate. We formulate a linear program (LP) whose size is proportional to the circuit size. This LP determines the inertial delay as well as input to output delays for each gate of the circuit with the given u b, such that all glitches are eliminated and the overall delay of the circuit is minimized. Because of the additional exibility in specifying gate delays, the glitch suppression is guaranteed without any delay bu ers. Hence this design consumes less power than those designed by other methods. We designed the circuit c1355 with 46 % of the original power dissipation compared toareference design. A previously published method, that characterizes each gate with a single delay, produced a c1355 circuit consuming 58% of the original power. Both low-power circuits had the same overall delay. The previous design required 224 delay bu ers, whereas the new design needed none. 1.

The problem of power-delay tradeoffs in transistor sizing is examined using a nonlinear optimization formulation. Both the dynamic and the short-circuit power are considered, and a new modeling technique is used to calculate the short-circuit power. The notion of transition density is used, with an enhancement that considers the effect of gate delays on the transition density. When the short-circuit power is neglected, the minimum power circuit is identical to the minimum area circuit. However, under our more realistic models, our experimental results on several circuits show that the minimum power circuit is not necessarily the same as the minimum area circuit.

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A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simplified linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, non-RC based transistor delay model was used which resulted in a non-convex relationship between the delay and the silicon area of a VLSI chip. Genetic algorithms are better suited for discrete, non-convex, non-linear optimization problems than traditional calculus-based algorithms. By using the genetic algorithms in the performance and area optimization, we are able to find the optimal values for both delay and silicon area for the ISCAS benchmark circuits. Key Words: Area and Performance optimization; Transistor Sizing; Genetic algorithms 1 Introduction The techniques for performance and area optimization of VLSI systems can be divi...

Abstract—Convex-optimization techniques are very popular in the very large-scale-integration design society due to their guaranteed convergence to a global optimal point. The table data need to be fitted into convex forms to be used in the convex optimization problems. Fitting the tables into posynomials, which are analytically convex under logarithmic transformation, may suffer from the excessive fitting errors as the fitting problem is nonconvex. In this paper, we propose to directly adjust the lookup-table values into a numerically convex lookup table without any explicit analytical form. We show that numerically “convexifying ” the lookup-table data with minimum perturbation can be formulated as a convex semidefinite optimization problem, and hence, optimality can be reached in polynomial time. We also propose three algorithms to make the table data smooth to enable faster convergence of the convex optimizer. Results from extensive experiments on industrial cell libraries demonstrate 9.6 × improvement in fitting error over a welldeveloped posynomial-fitting procedure. We illustrate the effectiveness of this model in a convex optimization problem by providing results for using our model in the optimal gate sizing of standard cells. We observe a 5.07 % improvement in the delay of International Symposium on Circuits and Systems (ISCAS) benchmark circuits over the posynomial-fitting procedure. Index Terms—Convex optimization, gate sizing, semidefinite programming. I.

Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically done manually, and is often custom style. This adversely impacts the overall productivity of the design team, as well as the quality of the design. In spite of this, very little automation has been available to the designers of high performance datapaths. In this paper we present a new "macrodriven " approach to the design of datapath circuits. Our approach, referred to as SMART (Smart Macro Design Advisor), is based on automatic generation of regular datapath components such as muxes, comparators, adders etc., which we refer to as datapath macros. The generated solution is based on designer provided constraints such as delay, load and slope, and is optimized for a designer provided cost metric such as power, area. Results on datapath circuits of a high-performance microprocessor show that this approach is very effective for both designer productivity as well as design quality.

A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a sufficient set of constraints to ensure that, when all slacks are non-negative, the corresponding circuit will be free of late signal timing problems. Cycle stealing is directly permitted by the formulation. However, moderate restrictions may be necessary to ensure that the timing constraint graph is acyclic. Forcing the constraint graph to be acyclic allows a broad range of existing optimization algorithms to be easily extended to better optimize circuits with level-sensitive latches. We describe the extension of two such algorithms, both of which attempt to solve the problem of selecting parts from a library to minimize area subject to a cycle time constraint. 1 The critical path method and timing-driven design When a circuit must be designed to satisfy stringent timing constraints, we say that the design is timing-driven. Researchers have described a wide variety of timingdriven design problems: logic synthesis, retiming, transistor sizing, part selection, input ordering, and placement and routing. Despite the range and variety of these problems, each approach is derived from a common framework for representing and enforcing timing constraints: the Critical Path Method (CPM) [1]. The application of CPM and a related technique called PERT to digital circuits was first described by Kirkpatrick and Clark [2] and later by Hitchcock, Smith, and Cheng [3]. In this paper, circuits are represented by a graph in which directed arcs represent delays and nodes represent electrically equipotential regions. Two special nodes, the source and sink, group circuit inputs and outputs, respectively. The circuit computation time is obtained by making a single pass through the graph. Beginning with the source

The paper introduces a novel methodology to obtain the entire arealpower consumption versus delay tradeoff curve for the crit-ical path of a combinational logic circuit in a very efficient way. Compared to other proposed ways based on the optimization of the whole circuit for every point of the tradeoff curve, in this work only a subset of the boolean network representing the circuit is optimized each time. Performance comparison and results based on the MCNC'91 set of two-level benchmark circuits are given. It is demonstrated that the proposed methodology produces trade-off curves for large circuits of thousands of gates greatly reducing the computation complexity (measured in number of variables of an equivalent linear programming problem) by a factor up to 16 times. 1.

Introduction: The design of digital circuits, especially for full-custom cells, is often a time consuming and laborious process relying on the intuition and heuristic knowledge of the designer. Optimising transistor sizes is the main key in meeting the various design specifications such as time-delay, area and power. The problem with this type of design optimisation is the large number of design variables leading to an explosion in the design space. Various solutions to these problems have been proposed which are based on the use of either static timing models [1], dynamic timing models [2] or a combination of the two [3]. Static timing models, while efficient in computation, do not take all transition states into account, resulting in low accuracy. Dynamic timing models, on the other hand, require the consideration of all possible input combinations and therefore suffer from the dimensionality problem. We propose to use a set of techniques known as design of experiments (DOE)

We present a framework for combining Voltage Scaling and Gate sizing techniques for power optimizations. Our results show that the combination of the two techniques perform better than the techniques applied in isolation. We introduce a new heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the loading capacitance of the gates. Our results show an average power reduction of 73 % when decisions are taken assuming dynamic power only and an average power reduction of 77 % when decisons include the short circuit power dissipation. The circuit under consideration are delay contrained and first optimized for delay under the environment of SIS. 1 Introduction Advances in se...