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Sorting Selection and Routing on the Array with Reconfigurable Optical Buses
"... In this paper we present efficient algorithms for sorting, selection and packet routing on the AROB (Array with Reconfigurable Optical Buses) model. ..."
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Cited by 32 (5 self)
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In this paper we present efficient algorithms for sorting, selection and packet routing on the AROB (Array with Reconfigurable Optical Buses) model.
Packet Routing In FixedConnection Networks: A Survey
, 1998
"... We survey routing problems on fixedconnection networks. We consider many aspects of the routing problem and provide known theoretical results for various communication models. We focus on (partial) permutation, krelation routing, routing to random destinations, dynamic routing, isotonic routing ..."
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Cited by 29 (3 self)
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We survey routing problems on fixedconnection networks. We consider many aspects of the routing problem and provide known theoretical results for various communication models. We focus on (partial) permutation, krelation routing, routing to random destinations, dynamic routing, isotonic routing, fault tolerant routing, and related sorting results. We also provide a list of unsolved problems and numerous references.
Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing, Sorting, and Selection
 In proc. 1st European Symp. on Algorithms
, 1993
"... Mesh connected computers have become attractive models of computing because of their varied special features. In this paper we consider two variations of the mesh model: 1) a mesh with fixed buses, and 2) a mesh with reconfigurable buses. Both these models have been the subject matter of extensive p ..."
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Cited by 25 (10 self)
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Mesh connected computers have become attractive models of computing because of their varied special features. In this paper we consider two variations of the mesh model: 1) a mesh with fixed buses, and 2) a mesh with reconfigurable buses. Both these models have been the subject matter of extensive previous research. We solve numerous important problems related to packet routing, sorting, and selection on these models. In particular, we provide lower bounds and very nearly matching upper bounds for the following problems on both these models: 1) Routing on a linear array; and 2) k \Gamma k routing and k \Gamma k sorting on a 2D mesh for any k 12. We provide an improved algorithm for 1 \Gamma 1 routing and a matching sorting algorithm. In addition we present greedy algorithms for 1 \Gamma 1 routing, k \Gamma k routing, and k \Gamma k sorting that are better on average and supply matching lower bounds. We also show that sorting can be performed in logarithmic time on a mesh with fixed bu...
Sorting and Selection on Interconnection Networks
 DIMACS Series in Discrete Mathematics and Theoretical Computer Science
, 1995
"... ABSTRACT. In this paper we identify techniques that havebeen employed in the design of sorting and selection algorithms for various interconnection networks. We consider both randomized and deterministic techniques. Interconnection Networks of interest include the mesh, the mesh with xed and recon g ..."
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Cited by 21 (15 self)
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ABSTRACT. In this paper we identify techniques that havebeen employed in the design of sorting and selection algorithms for various interconnection networks. We consider both randomized and deterministic techniques. Interconnection Networks of interest include the mesh, the mesh with xed and recon gurable buses, the hypercube family, and the star graph. For the sake of comparisons, we also list PRAM algorithms. 1
The Complexity of Reconfiguring Network Models
, 1992
"... This paper concerns some of the theoretical complexity aspects of the reconfigurable network model. The computational power of the model is investigated under several variants, depending on the type of switches (or switch operations) assumed by the network nodes. Computational power is evaluated by ..."
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Cited by 19 (5 self)
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This paper concerns some of the theoretical complexity aspects of the reconfigurable network model. The computational power of the model is investigated under several variants, depending on the type of switches (or switch operations) assumed by the network nodes. Computational power is evaluated by focusing on the set of problems computable in constant time in each variant. A hierarchy of such problem classes corresponding to different variants is shown to exist and is placed relative to traditional classes of complexity theory. Department of Mathematics and Computer Science, The Haifa University, Haifa, Israel. Email: yosi@mathcs2.haifa.ac.il y Department of Computer Science, Technische Universitat Munchen, 80290 Munchen, Germany. Email: lange@informatik.tumuenchen.de z Department of Applied Mathematics and Computer Science, The Weizmann Institute, Rehovot 76100, Israel. Email: peleg@wisdom.weizmann.ac.il. Supported in part by an Allon Fellowship, by a Bantrell Fellowship an...
Constant Time Algorithms for Computational Geometry on the Reconfigurable Mesh
 IEEE Transactions on Parallel and Distributed Systems
, 1997
"... The reconfigurable mesh consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. In this paper, we show O(1) time so ..."
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Cited by 18 (2 self)
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The reconfigurable mesh consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors. Recently, this model has attracted a lot of attention. In this paper, we show O(1) time solutions to the following computational geometry problems on the reconfigurable mesh: allpairs nearest neighbors, convex hull, triangulation, twodimensional maxima, twoset dominance counting, and smallest enclosing box. All these solutions accept N planar points as input and employ an N  N reconfigurable mesh. The basic scheme employed in our implementations is to recursively find an O(1) time solution. The number of recursion levels and the size of the subproblems at each level of recursion are optimized such that the problem decomposition and the solution to the problem can be obtained in constant time. As a result, we have developed some efficient merge techniques to combine th...
Timings for Associative Operations on the MASC Model
, 2001
"... The MASC (Multiple Associative Computing) model is a generalized associativestyle computational model that naturally supports massive dataparallelism and also controlparallelism. A wide range of applications has been developed on this model. Recent research has compared its power to the power of ..."
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Cited by 17 (8 self)
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The MASC (Multiple Associative Computing) model is a generalized associativestyle computational model that naturally supports massive dataparallelism and also controlparallelism. A wide range of applications has been developed on this model. Recent research has compared its power to the power of other popular parallel models such as the PRAM and MMB models using simulations. However, the simulation of MMB has identified some important issues regarding the cost of certain basic MASC operations required for associative computing such as broadcasts, reductions, and associative searches. This paper investigates these issues and gives background information and an analysis of timings for these operations, based on implementation techniques and comparison fairness with respect to other models. It aims to provide justification and clarify arguments on the timings for these constanttime or nearly constanttime basic MASC operations.
Supporting Sets of Arbitrary Connections on iWarp Through Communication Context Switches
 In Proc. SPAA
, 1993
"... In this paper we introduce the ConSet communication model for distributed memory parallel computers. The communication needs of an application program can be satisfied by some arbitrary set of connections which are partitioned into discrete phases. A communication context switch is used to select th ..."
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Cited by 15 (6 self)
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In this paper we introduce the ConSet communication model for distributed memory parallel computers. The communication needs of an application program can be satisfied by some arbitrary set of connections which are partitioned into discrete phases. A communication context switch is used to select the active phase. We present an implementation of the ConSet model on the iWarp and describe its performance characteristics, contrasting it to a message passing implementation on the same machine. Our implementation demonstrates how one existing parallel computer can function as a “reconfigurable network ” without needing a new processor interconnect technology. The ConSet model works best when communication patterns can be optimized at compile time. We examine the interactions of the target architecture with the algorithmic problems encountered designing a communication compiler to effectively partition, route, and schedule connections. We built a prototype communication compiler for our iWarp implementation, and are using it to generate iWarp code. Looking at basic communication patterns as well as patterns generated by an iterative finite element PDE solver, we compare ConSet’s performance (using the compiler’s schedules) to that of message passing. Our experiments suggestthat ConSet communication offers a performance advantage over messagepassing in applications where the communication pattern is known at compile time. 1
A Novel Deterministic Sampling Scheme with Applications to BroadcastEfficient Sorting on the Reconfigurable Mesh
 Journal of Parallel and Distributed Computing
, 1996
"... The main contribution of this work is to present a simple deterministic sampling strategy that, when used for bucket sorting, yields buckets that are remarkably well balanced, making costly balancing unnecessary. To the best of our knowledge this is the first instance of a deterministic sampling ..."
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Cited by 14 (3 self)
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The main contribution of this work is to present a simple deterministic sampling strategy that, when used for bucket sorting, yields buckets that are remarkably well balanced, making costly balancing unnecessary. To the best of our knowledge this is the first instance of a deterministic sampling strategy featuring this performance. Although the strategy is perfectly general, we illustrate its power by devising a VLSIoptimal, O(1) time sorting algorithm for the reconfigurable mesh. As a byproduct of the inherent simplicity of our sampling and bucketing scheme we show that our sorting algorithm can be implemented using only 35 broadcast operations, a substantial improvement over the previously best known algorithm that requires 59 broadcasts. Keywords: deterministic sampling, bucket sort, reconfigurable meshes, sorting, VLSI optimal algorithms, constanttime algorithms 1 Introduction Sorting is, unquestionably, one of the fundamental operations in computer science. A natura...
An Optimal Multiplication Algorithm on Reconfigurable Mesh
 IEEE Transactions on Parallel and Distributed Systems
, 1997
"... An O(1) time algorithm to multiply two Nbit binary numbers using an N N bitmodel of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representat ..."
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Cited by 13 (3 self)
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An O(1) time algorithm to multiply two Nbit binary numbers using an N N bitmodel of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representation and data movement and using multidimensional Rader Transform. The algorithm is extended to result in AT 2 optimality over 1 TN in a variant of the bitmodel of VLSI. Index TermsInteger multiplication, reconfigurable mesh, optimal algorithm, areatime trade off, VLSI architecture.  F  1I NTRODUCTION HE reconfigurable mesh is a twodimensional mesh of processors connected by reconfigurable buses [17]. Though the buses outside the Processing Elements (PEs) are fixed, the internal connection between the I/O ports of each PE can be reconfigured by individual PEs during the execution of algorithms. The reconfigurable mesh cap...