This paper addresses the important subject of estimating the worst-case execution time (WCET) of hard real-time programs essentially needed for further evaluation of realtime systems. Purely structure oriented methods, analysing the control flow of the program without taking into account functional dependencies, tend to overestimate the execution time. An exact solution of this NP-complete problem is impossible for larger applications. In this paper, we propose a new heuristic of finding an estimate on the WCET. It provides a reasonable trade-off between analysis results and analysis efforts: the results will still be better than purely structure oriented methods without spending too much time on finding an exact solution. For this purpose our approach does not need any user annotations except for maximum loop counts and maximum recursion depths. The actual algorithm combines pruned path enumeration with the concept of symbolic execution. 1. Introduction Predicting the execution times...

This paper addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at5 the inputs.) It is well known that using the length of the topologically longest path as an estimate of circuit delay may be pessimistic since this path may be false, i.e., it cannot propagate an event. Thus, the true delay corresponds to the length of the longest true path. This forces us to examine the conditions under which a path is true. We introduce the notion of static cosensitization of paths which leads us to necessary and sufficient conditions for determining the truth or falsity of a single path, or a set of paths. We apply these results to develop a delay computation algorithm that has the unique feature that it is able to determine the truth or falsity of entire sets of paths simultaneously. This algorithm uses conventional stuck-at-fault testing techniques to arrive at a delay computation method that is both correct and computationally practical, even for particularly difficult circuits.

The existence of false paths represents a significant

In this report we introduce a new proof-theoretic approach to the semantics of Constraint Logic Programming, based on an intuitionistic first-order modal logic, called QLL. The distinguishing feature of this new approach is that the logic calculus of QLL is used not only to capture the usual extensional aspects of Logic Programming, i.e. "which queries are successful, " but also some of the intensional aspects, i.e. "what is the answer constraint and how is it constructed." It provides for a direct link between the model-theoretic and the operational semantics following a formulas-as-programs and proofs-as-constraints principle. This approach makes use of logic in a different way than other approaches based on logic calculi. On the one side it is to be distinguished from the well-known provability semantics which is concerned merely with what is derivable as opposed to how it is derivable, paying attention to the fact that it is the how that determines the answer constraint. ...

This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADD's). The procedure we propose, implemented as an extension of the SIS synthesis system, is able to provide more accurate timing information than any other method presented so far; in particular, it is able to compute and store the true delay of the gate-level representation of the circuit for all possible input vectors, as opposed to the traditional methods which consider only the worst-case primary inputs combination. Furthermore, the approach does not require any explicit false path elimination. The information calculated by the timing analyzer has several practical applications such as determining the sets of critical input vectors, critical gates, and critical paths of the circuit, which may be efficiently used in the process of resynthesizing the network for low-power consumption.

Logic synthesis is the process of automatically generating optimized logic level representation from a high-level description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time, while achieving performance objectives. This paper describes the IBM logic synthesis system BooleDozer TM; including its organization, main algorithms and how it ts into the design process. The BooleDozer logic synthesis system has been widely used within IBM to successfully synthesize processor and ASIC designs. 1

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We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Based on the conditional delay matrix (CDM) formalism we introduced earlier, the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. The signal propagation conditions are restricted to a set of predefined control inputs, which results in significant reductions in the size of the conditions as well as computation time. We have implemented ACD and experimented with reverse-engineered high-level versions of the ISCAS-85 benchmarks. Our results demonstrate up to three orders of magnitude speedup in computation time over exact methods, with little or no loss in accuracy. 1 Introduction The exact timing analysis methods used to calculate delays in logic circuits tend to be computationally expensive. In symbolic methods [1, 6, 12], the signal propagation conditions can grow too rapidly with circuit size, while in search-based ...

This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on topological delay analysis without any consideration of false paths. In this paper, however, we take into account false paths between the intermediate nodes and the primary outputs explicitly to characterize the timing constraints at the nodes more accurately. We show that this approach leads to a technique for computing a more refined and relaxed timing constraint than that obtained by topological analysis. We generalize the notion of required times from a single constant to a relation where a signal is required at different times depending on the values of the other signals.

We propose a hierarchical timing analysis technique for combinational circuits under the tightest known sensitization criterion, the XBD0 delay model. Given a hierarchical combinational circuit, a generalized delay model of each leaf module is characterized first. Since this timing characterization step takes into account false paths in each module, the delay model is more accurate than the one obtained by topological analysis. Then topological delay analysis is performed on the circuit composed of generalized gates replacing the leaf modules, where the "gate" delay model is the derived one. As far as the authors know, this is the first result that shows that hierarchical analysis is possible under state-of-the-art tight sensitization criteria. We demonstrate by experimental results that loss of accuracy in using the hierarchical approach is very minimal in practice. The theory developed in this paper also provides a foundation for incremental timing analysis under accurate sensitizati...