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On the False Path Problem in Hard RealTime Programs
 In Proceedings of the 8th Euromicro Workshop on Realtime Systems
, 1996
"... This paper addresses the important subject of estimating the worstcase execution time (WCET) of hard realtime programs essentially needed for further evaluation of realtime systems. Purely structure oriented methods, analysing the control flow of the program without taking into account functional ..."
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Cited by 59 (8 self)
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This paper addresses the important subject of estimating the worstcase execution time (WCET) of hard realtime programs essentially needed for further evaluation of realtime systems. Purely structure oriented methods, analysing the control flow of the program without taking into account functional dependencies, tend to overestimate the execution time. An exact solution of this NPcomplete problem is impossible for larger applications. In this paper, we propose a new heuristic of finding an estimate on the WCET. It provides a reasonable tradeoff between analysis results and analysis efforts: the results will still be better than purely structure oriented methods without spending too much time on finding an exact solution. For this purpose our approach does not need any user annotations except for maximum loop counts and maximum recursion depths. The actual algorithm combines pruned path enumeration with the concept of symbolic execution. 1. Introduction Predicting the execution times...
Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms
 IEEE TRANSACTIONS ON CAD
, 1993
"... This paper addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at5 the inputs.) It is well known that using the length of the topologic ..."
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Cited by 36 (1 self)
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This paper addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at5 the inputs.) It is well known that using the length of the topologically longest path as an estimate of circuit delay may be pessimistic since this path may be false, i.e., it cannot propagate an event. Thus, the true delay corresponds to the length of the longest true path. This forces us to examine the conditions under which a path is true. We introduce the notion of static cosensitization of paths which leads us to necessary and sufficient conditions for determining the truth or falsity of a single path, or a set of paths. We apply these results to develop a delay computation algorithm that has the unique feature that it is able to determine the truth or falsity of entire sets of paths simultaneously. This algorithm uses conventional stuckatfault testing techniques to arrive at a delay computation method that is both correct and computationally practical, even for particularly difficult circuits.
Timing Analysis Using Propositional Satisfiability
 in IEEE International Conference on Electronics, Circuits and Systems
, 1998
"... The existence of false paths represents a significant ..."
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Cited by 16 (8 self)
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The existence of false paths represents a significant
Booledozer: Logic synthesis for ASICs
 IBM Journal of Research and Development
, 1996
"... Logic synthesis is the process of automatically generating optimized logic level representation from a highlevel description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design ..."
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Cited by 14 (2 self)
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Logic synthesis is the process of automatically generating optimized logic level representation from a highlevel description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time, while achieving performance objectives. This paper describes the IBM logic synthesis system BooleDozer TM; including its organization, main algorithms and how it ts into the design process. The BooleDozer logic synthesis system has been widely used within IBM to successfully synthesize processor and ASIC designs. 1
Timing Analysis of Combinational Circuits using ADD's
, 1994
"... This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADD's). The procedure we propose, implemented as an extension of the SIS synthesis system, is able to ..."
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Cited by 13 (3 self)
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This paper presents a symbolic algorithm to perform timing analysis of combinational circuits which takes advantage of the high compactness of representation of the Algebraic Decision Diagrams (ADD's). The procedure we propose, implemented as an extension of the SIS synthesis system, is able to provide more accurate timing information than any other method presented so far; in particular, it is able to compute and store the true delay of the gatelevel representation of the circuit for all possible input vectors, as opposed to the traditional methods which consider only the worstcase primary inputs combination. Furthermore, the approach does not require any explicit false path elimination. The information calculated by the timing analyzer has several practical applications such as determining the sets of critical input vectors, critical gates, and critical paths of the circuit, which may be efficiently used in the process of resynthesizing the network for lowpower consumption.
Automatic synthesis of large telescopic units based on nearminimum timed supersetting
 IEEE Trans. on Comp
, 1999
"... AbstractÐIn highperformance systems, variablelatency units are often employed to improve the average throughput when the worstcase delay exceeds the cycle time. Traditionally, units of this type have been handdesigned. In this paper, we propose a technique for the automatic synthesis of variable ..."
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Cited by 13 (0 self)
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AbstractÐIn highperformance systems, variablelatency units are often employed to improve the average throughput when the worstcase delay exceeds the cycle time. Traditionally, units of this type have been handdesigned. In this paper, we propose a technique for the automatic synthesis of variablelatency units that is applicable to large datapath modules. We define and study an optimization problem, timed supersetting, whose solution is at the kernel of the procedure for automatic generation of variablelatency units. We contribute a new algorithm for solving timed supersetting in the most difficult case, that is, when the timing behavior of the circuit is expressed through an accurate delay model. The proposed solution overcomes the computational limitations of previous approaches and its robustness is experimentally demonstrated by obtaining highthroughput, variablelatency implementations for all the largest circuits in the Iscas '85 and Iscas '89 benchmark suites, as well as for some realistic, highperformance arithmetic units. Index TermsÐLogic synthesis, timing analysis, throughput optimization. æ 1
Firstorder Lax Logic as a Framework for Constraint Logic Programming
, 1997
"... In this report we introduce a new prooftheoretic approach to the semantics of Constraint Logic Programming, based on an intuitionistic firstorder modal logic, called QLL. The distinguishing feature of this new approach is that the logic calculus of QLL is used not only to capture the usual exte ..."
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Cited by 12 (4 self)
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In this report we introduce a new prooftheoretic approach to the semantics of Constraint Logic Programming, based on an intuitionistic firstorder modal logic, called QLL. The distinguishing feature of this new approach is that the logic calculus of QLL is used not only to capture the usual extensional aspects of Logic Programming, i.e. "which queries are successful, " but also some of the intensional aspects, i.e. "what is the answer constraint and how is it constructed." It provides for a direct link between the modeltheoretic and the operational semantics following a formulasasprograms and proofsasconstraints principle. This approach makes use of logic in a different way than other approaches based on logic calculi. On the one side it is to be distinguished from the wellknown provability semantics which is concerned merely with what is derivable as opposed to how it is derivable, paying attention to the fact that it is the how that determines the answer constraint. ...
Timing analysis with known false subgraphs
 IEEE/ ACM International Conference on ComputerAided Design
, 1995
"... Abstract In this paper we formulate the problem of timing analysis with known false sub graphs. This problem is important when we want the timing analysis system to take into account false path information that is supplied either by the user or by another program, and supply accurate timing informa ..."
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Cited by 10 (0 self)
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Abstract In this paper we formulate the problem of timing analysis with known false sub graphs. This problem is important when we want the timing analysis system to take into account false path information that is supplied either by the user or by another program, and supply accurate timing information to optimization programs such as placement and wiring. We present an efficient algorithm for the problem.
An Approximate Timing Analysis Method for Datapath Circuits
, 1996
"... We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Based on the conditional delay matrix (CDM) formalism we introduced earlier, the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. ..."
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Cited by 9 (0 self)
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We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Based on the conditional delay matrix (CDM) formalism we introduced earlier, the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. The signal propagation conditions are restricted to a set of predefined control inputs, which results in significant reductions in the size of the conditions as well as computation time. We have implemented ACD and experimented with reverseengineered highlevel versions of the ISCAS85 benchmarks. Our results demonstrate up to three orders of magnitude speedup in computation time over exact methods, with little or no loss in accuracy. 1 Introduction The exact timing analysis methods used to calculate delays in logic circuits tend to be computationally expensive. In symbolic methods [1, 6, 12], the signal propagation conditions can grow too rapidly with circuit size, while in searchbased ...