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Power Minimization in IC Design: Principles and Applications
 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 1996
"... Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low powe ..."
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Cited by 190 (28 self)
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Low power has emerged as a principal theme in today’s electronics industry. The need for low power has caused a major paradigm shift in which power dissipation is as important as performance and area. This article presents an indepth survey of CAD methodologies and techniques for designing low power digital CMOS circuits and systems and describes the many issues facing designers at architectural, logic and physical levels of design abstraction. It reviews some of the techniques and tools that have been proposed to overcome these difficulties and outlines the future challenges that must be met to design low power, high performance systems.
Efficient Estimation of Dynamic Power Consumption under a Real Delay Model
 IEEE Internations Conference on ComputerAided Design
, 1993
"... In CMOS circuits, glitches account for a sizable part of the total power consumption. In this paper, we present a fast and memory efficient power estimation technique for cmos circuits which estimates the power consumed due to the glitches. Our technique is based on the notion of tagged transition w ..."
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Cited by 44 (0 self)
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In CMOS circuits, glitches account for a sizable part of the total power consumption. In this paper, we present a fast and memory efficient power estimation technique for cmos circuits which estimates the power consumed due to the glitches. Our technique is based on the notion of tagged transition waveforms. In particular, we approximate the correlation between transition waveforms for two signal lines by the correlation between the steady state values of these lines. We obtain an order of magnitude speed up over an exact method with an average error of only 1%. 1 Introduction With recent advances in microelectronic technology, smaller devices are now possible allowing more functionality on an integrated circuit (ic). Portable applications have shifted from conventional low performance products such as wristwatches and calculators to high throughput and computationally intensive products such as notebook computers and personal digital assistants. The new applications require high spe...
Power Efficient Technology Decomposition and Mapping under an Extended Power Consumption Model
, 1994
"... We propose a new power consumption model which accounts for the power consumption at the internal nodes of a cmos gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first ..."
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Cited by 26 (7 self)
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We propose a new power consumption model which accounts for the power consumption at the internal nodes of a cmos gate. Next, we address the problem of minimizing the average power consumption during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first step, we generate a nand decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum. In the second step, we perform a power efficient technology mapping that finds a minimal power mapping for given timing constraints (subject to the unknown load problem). 1 Introduction With recent advances in microelectronic technology, smaller devices are now possible allowing more functionality on an integrated circuit (ic). Portable applications have shifted from conventional low performance products such as wristwatches and calculators to high throughput and computationally intensive products such as notebook computers and cellul...
Lowpower design methodology and applications utilizing dual supply voltages
 Proceedings of the Asia and South Pacific Design Automation Conference
, 2000
"... Abstract This paper describes a gatelevel power minimization methodology using dual supply voltages. Gates and flipflops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dualV DD circuit synthesis and P&R. We give a brief overview ..."
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Cited by 20 (0 self)
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Abstract This paper describes a gatelevel power minimization methodology using dual supply voltages. Gates and flipflops off the critical paths are made to operate at the reduced supply voltage to save power. Core technologies are dualV DD circuit synthesis and P&R. We give a brief overview on existing lowpower EDA technologies as background and discuss advantages and challenges of the dualVDD approach. Through real design examples, we will show that the approach reduces power effectively while keeping the performance at ne gligible area overhead. I.
Low Power Architectural Design Methodologies
 PH.D THESIS, MEMORANDUM NO. UCB/ERL M94/62, 30TH
, 1994
"... In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another de ..."
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Cited by 17 (0 self)
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In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, batteryoperated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom  and complexity  to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support lowpower system design. Lowpower techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and systemlevel optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the registertransfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switchlevel accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.
Design Technologies for Low Power VLSI
 In Encyclopedia of Computer Science and Technology
, 1997
"... Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing l ..."
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Cited by 15 (0 self)
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Low power has emerged as a principal theme in today's electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems.
An Integrated CAD Environment for LowPower Design
 IEEE Design and Test of Computers
, 1995
"... A CAD environment for lowpower design is presented. The environment supports a highlevel approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. This methodology is consistent with current stateoftheart techniques for lowpower design. The ..."
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Cited by 11 (0 self)
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A CAD environment for lowpower design is presented. The environment supports a highlevel approach to power reduction, emphasizing optimizations at the algorithm and architecture levels of abstraction. This methodology is consistent with current stateoftheart techniques for lowpower design. The framework consists of a set of analysis and optimization tools that span the design hierarchy. These tools are integrated in a way that allows the designer to employ a systematic approach to lowpower design through a topdown exploration and refinement of solutions in the areatimepower (ATP) design space. The efficacy of the CAD environment and tools is illustrated by a case study which leads to a lowpower implementation of a digital bandpass filter. The proposed approach is shown to lead to more than an order of magnitude savings in power. This result is achieved by a thorough search of the areatimepower design space, which would not have been possible without the assistance of highl...
Poweraware placement
 In Proceedings of the 42nd annual conference on Design automation (DAC
, 2005
"... Lowering power is one of the greatest challenges facing the IC industry today. We present a poweraware placement method that simultaneously performs (1) activitybased register clustering that reduces clock power by placing registers in the same leaf cluster of the clock trees in a smaller area and ..."
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Cited by 9 (1 self)
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Lowering power is one of the greatest challenges facing the IC industry today. We present a poweraware placement method that simultaneously performs (1) activitybased register clustering that reduces clock power by placing registers in the same leaf cluster of the clock trees in a smaller area and (2) activitybased net weighting that reduces net switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. The method applies to designs with multiple clocks and gated clocks. We implemented the method and obtained experimental results on 8 realworld designs after placement, routing, extraction and analysis. The poweraware placement method achieved on average 25.3 % and 11.4 % reduction in net switching power and total power respectively, with 2.0 % timing, 1.2 % cell area and 11.5% runtime impact. This method has been incorporated into a commercial physical design tool.
Fast Approximation Algorithms on Maxcut, kColoring and kColor Ordering for VLSI Applications
, 1994
"... There is a number of VLSI problems that have a common structure. We investigate such a structure that leads to a unified approach for three independent VLSI layout problems: partitioning, placement and via minimization. Along the line, we first propose a lineartime approximation algorithm on maxcut ..."
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Cited by 6 (0 self)
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There is a number of VLSI problems that have a common structure. We investigate such a structure that leads to a unified approach for three independent VLSI layout problems: partitioning, placement and via minimization. Along the line, we first propose a lineartime approximation algorithm on maxcut and two closely related problems: k coloring and maximal kcolor ordering problem. The kcoloring is a generalization of the maxcut and the maximal kcolor ordering is a generalization of the kcoloring. For a graph G with e edges and n vertices, our maxcut approximation algorithm runs in O(e + n) sequential time yielding a nodebalanced maxcut with size at least (w(E) + w(E)=n)=2, improving the time complexity of O(e log e) known before. Building on the proposed maxcut technique and employing a heightbalanced binary decomposition, we devise an O((e + n) log k) time algorithm for the kcoloring problem which always finds a kpartition of vertices such that the number of bad (or "defec...
On Reducing Transitions Through Data Modifications
"... Since busses take up significant fraction of chiparea, the bus capacitances are often considerable, and the bus power may account for as much as 40 % of the total power consumed on the chip [5]. In applications where the integrity of data is not very important, data may bechanged by 3 to 5 % withou ..."
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Cited by 4 (0 self)
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Since busses take up significant fraction of chiparea, the bus capacitances are often considerable, and the bus power may account for as much as 40 % of the total power consumed on the chip [5]. In applications where the integrity of data is not very important, data may bechanged by 3 to 5 % without losing too much information. One such application is that of a binaryencoded image, in which case the human eye cannot perceive the small change. However, these small changes can signi cantly reduce the number of transitions on the data bus and thus the power/energy consumed. We address the following problem: Given a sequence of nkbit data words and an errortolerance e % (i.e., at most e % of the data bits are permitted to change), select the bits to be modified so that the total number of transitions is minimized. We show that a greedy strategy is not always optimum. We propose a lineartime dynamic programming based algorithm that generates an optimum solution to this problem. The experimental results for randomly generated data with a uniform distribution indicate that by changing e % data bits, the transitions can be reduced, on average, by 4e%.