VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro

Abstract. In this paper we present two algorithms for the floorplan design problem. The algorithms are quite similar in spirit. They both use Polish expressions to represent floorplans and employ the search method of simulated annealing. The first algorithm is for the case where all modules are rectangular, and the second one is for the case where the modules are either rectangular or L-shaped. Our algorithms consider simultaneously the interconnection information as well as the area and shape information for the modules. Experimental results indicate that our algorithms perform well for many test problems. Key Words. VLSI circuit layout, Floorplan design, Simulated annealing.

This dissertation examines a number of geometric interconnection, partitioning, and placement problems arising in the field of VLSI physical design automation. In particular, many of the results concern the geometric Steiner tree problem: given a set of terminals in the plane, find a minimum-length interconnection of those terminals according to some geometric distance metric. Two new algorithms are introduced that compute optimal rectilinear Steiner trees. Both are provably faster than any previous algorithm for instances small enough to solve in practice, and both are also fast in practice. The first algorithm is a dynamic programming algorithm based on decomposing a rectilinear Steiner tree into full trees. A full tree is a Steiner tree in which every terminal is a leaf. Its time complexity is O(n3^n), where n is the number of terminals. The second algorithm modifies the first by the use of full-set screening, which is a process by which some candidate full trees are eliminated f...

Floorplanning is a crucial phase in VLSI Physical Design. The subsequent placement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is Simulated Annealing. It gives very good floorplanning results but has major limitation in terms of running time. For more than tens of modules Simulated Annealing is not practical. Floorplanning forms the core of many synthesis applications. Designers need faster prediction of system metrics to quickly evaluate the effects of design changes. Early prediction of metrics is imperative for estimating timing and routability. In this work we propose a constructive technique for predicting floorplan metrics. We show how to modify the existing top-down partitioning based floorplanning to obtain a fast and accurate floorplan prediction. The prediction gets better as number of modules and flexibility in their shapes increases. We also explore the applicability of traditional Sizing Theorem when combining two modules based on their sizes and interconnecting wirelength. Experimental results show that our prediction algorithm can predict the area/length cost function normally within 5-10% of the results obtained by Simulated Annealing and is, on the average, thousand times faster.

The placement problem in the layout design of electronic circuits consists of finding a nonoverlapping assignment of rectangular cells to positions on the chip so that wireability is guaranteed and certain technical constraints are met. This problem can be modelled as a quadratic 0/1-program subject to linear constraints. We will present a decomposition approach to the placement problem and give results about.A/^P-hardness and the existence of e-approximative algorithms for the involved optimization problems. A graphtheoretic formulation of these problems will enable us to develop approximative algorithms. Finally we will present details of the implementation of our approach and compare it to industrial state of the art placement routines.

I hereby declare that I am the sole author of this thesis. I authorize the University of Guelph to lend this thesis to other institutions or individuals for the purpose of scholarly research. I further authorize the University of Guelph to reproduce this thesis by photo-copying or by other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. ii The University of Guelph requires the signatures of all persons using or photo-copying this thesis. Please sign below, and give address and date. iii iv A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the next decade. This tremendous growth is made possible by the development of sophisticated design tools and software. To deal with the complexity

The standard cell placement problem has been extensively studied in the past twenty years. Many approaches were proposed and proven effective in practice. However, successful placement tools need enormous time in the course of development. In this paper we propose a new snap-on placement tool, which is based on multilevel hierarchical placement method. It has great flexibility to combine existing packages and techniques in its top-down framework. In addition, it can be used to build a good placement tool in a short amount of time. Some important issues in multilevel hierarchical placement are discussed here. We investigate the behavior of net-cut and wirelength objectives in global placement problem, propose a +ffi level clustering technique and design a new topdown placement method based on partitioning, annealing and +ffi level technique. We also work on the trade-off between solution quality and running time during the hierarchical placement. Experimental results show the strength ...

In this paper, we present a new method for cell placement. The method is based on a new metric for wirelength that ensures no overlap among cells sharing common nets (repeller model). Moreover, new forces working on the cells are added to the new metric to attract the cells to the less dense regions and help spread out the cells within the placement area. Minimizing traditional metrics (linear or quadratic) results in a placement with substantial amount of overlap. The methodology iterates between global optimization and slicing the placement area to diminish cell overlap and attain uniform distribution of the cells within the placement floor. To help cells spread out, hard constraints are added to the problem in each iteration resulting in a further constrained version of the original problem. Unlike these approaches, no hard constraints are required in the new approach. Besides, the new metric is convex and versatile in the sense that it can be applied to placement problems with no fixed cells (i.e, FPGAs).

MinCut algorithms have received much attention in the past for treating the placement problem in layout synthesis. The paper introduces a new class of MinCut partitioning algorithms (SQP) meeting global minimization requirements. The new class of algorithms in its different variations is empirically compared with the classical MinCut procedures as well as with recent extensions. The new algorithms have shown a significant (10 to 40%) improvement in the overall netlength compared with known algorithms. Moreover, the new class of algorithms is proved to have a linear time complexity. 1 Introduction In automatic layout synthesis of VLSI chips one commonly distinguishes two different design stages. The first one is placement that is followed by the routing stage. However, the placement stage is heavily responsible for allowing the routing stage to find a complete routing in a reasonable amount of time. One of the most popular placement algorithms have been the class of MinCut algorithms ...

last several years, and promises to continue to do so. If circuit design is to keep pace with fabrication technology, radically new approaches to computer-aided design will be necessary. One appealing approach is general purpose parallel processing. This thesis explores the issues involved in developing a framework for circuit simulation which exploits the locality exhibited by circuit operation to achieve a high degree of parallelism. This framework maps the topology of the circuit onto the multiprocessor, assigning the simulation of individual partitions to separate processors. A new form of synchronization is developed, based upon a history maintenance and roll back strategy. The circuit simulator PRSIM was designed and implemented to determine the efficacy of this approach. The results of several preliminary experiments are reported, along with an analysis of the behavior of PRSIM.