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28
Scalable certification of native code: Experience from compiling to TALx86
, 2000
"... Abstract Certifying compilation allows a compiler to produce annotations that prove that target code abides by a specified safety policy. An independent verifier can check the code without needing to trust the compiler. For such a system to be generally useful, the safety policy should be expressive ..."
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Cited by 5 (1 self)
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Abstract Certifying compilation allows a compiler to produce annotations that prove that target code abides by a specified safety policy. An independent verifier can check the code without needing to trust the compiler. For such a system to be generally useful, the safety policy should be expressive enough to allow different compilers to effectively produce certifiable code. In this work, we use our experience in writing a certifying compiler to suggest general design principles that should allow concise yet expressive certificates. As an extended example, we present our compiler's translation of the control flow of Popcorn, a high-level language with function pointers and exception handlers, to TALx86, a typed assembly language with registers, a stack, memory, and code blocks. This example motivates techniques for controlling certificate size and verification time. We quantify the effectiveness of techniques for reducing the overhead of certifying compilation by measuring the effects their use has on a real Popcorn application, the compiler itself. The selective use of these techniques, which include common-subexpression elimination of types, higherorder type abbreviations, and selective re-verification, can change certificate size and verification time by well over an order of magnitude. We consider this report to be the first quantitative study on the practicality of certifying a real program using a type system not specifically designed for the compiler or source language. 1 Background A certifying compiler takes high-level source code and produces target code with a certificate that ensures that the target code respects a desired safety or security policy. To date, certifying compilers have primarily concentrated on producing certificates of type safety. For example, Sun's javac compiler maps Java source code to statically typed Java Virtual Machine Language (JVML) code. The JVML code includes typing annotations that a dataflow analysisbased verifier can use to ensure that the code is type safe.
Parallel Graph Coloring Algorithms Using OpenMP (Extended Abstract)
- In First European Workshop on OpenMP
"... Assefaw Hadish Gebremedhin* Fredrik Manne i 1 ..."
Compiler Implementation in a Formal Logical Framework
- In Proceedings of the 2003 workshop on Mechanized
, 2003
"... The task of designing and implementing a compiler can be a dicult and error-prone process. In this paper, we present a new approach based on the use of higher-order abstract syntax and term rewriting in a logical framework. All program transformations, from parsing to code generation, are cleanly is ..."
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Cited by 4 (2 self)
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The task of designing and implementing a compiler can be a dicult and error-prone process. In this paper, we present a new approach based on the use of higher-order abstract syntax and term rewriting in a logical framework. All program transformations, from parsing to code generation, are cleanly isolated and specified as term rewrites. This has several advantages. The correctness of the compiler depends solely on a small set of rewrite rules that are written in the language of formal mathematics. In addition, the logical framework guarantees the preservation of scoping, and it automates many frequently-occurring tasks including substitution and rewriting strategies. As we show, compiler development in a logical framework can be easier than in a general-purpose language like ML, in part because of automation, and also because the framework provides extensive support for examination, validation, and debugging of the compiler transformations. The paper is organized around a case study, using the MetaPRL logical framework to compile an ML-like language to Intel x86 assembly. We also present a scoped formalization of x86 assembly in which all registers are immutable.
Retargetable Graph-Coloring Register Allocation for Irregular Architectures
- COMPUTERS AND CHEMICAL ENGINEERING
, 2003
"... Global register allocation is one of the most important optimizations in a compiler. Since the early 80's, register allocation by graph coloring has been the dominant approach. The traditional formulation of graph-coloring register allocation implicitly assumes a single bank of non-overlapping g ..."
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Cited by 4 (0 self)
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Global register allocation is one of the most important optimizations in a compiler. Since the early 80's, register allocation by graph coloring has been the dominant approach. The traditional formulation of graph-coloring register allocation implicitly assumes a single bank of non-overlapping general-purpose registers and does not handle irregular architectural features like overlapping register pairs, special purpose registers, and multiple register banks. We present a generalization of graph-coloring register allocation that can handle all such irregularities. The algorithm
Native Code Compilation for Erlang
, 1996
"... We describe the design and implementation of a native compiler for Erlang, built on top of an existing emulated implementation. Many Erlang- programs are time-critical, and as Erlang becomes more widely used, the need for fast implementations increase. We show how simple native compilation can incr ..."
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Cited by 4 (1 self)
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We describe the design and implementation of a native compiler for Erlang, built on top of an existing emulated implementation. Many Erlang- programs are time-critical, and as Erlang becomes more widely used, the need for fast implementations increase. We show how simple native compilation can increase the speed of Erlang programs, even compared to Erlang programs compiled via C. Several benchmark programs are examined and the results analysed, showing that our simple method gives a considerable gain in execution speed over current implementations. Contents 1 Introduction 1 2 JAM 3 2.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Data Representation . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 Concurrency . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 The Compiler 6 3.1 Translation ...
Eliminating Redundancies in Sum-of-Product Array Computations
, 2001
"... Array programming languages such as Fortran 90, High Performance Fortran and ZPL are well-suited to scientic computing because they free the scientist from the responsibility of managing burdensome low-level details that complicate programming in languages like C and Fortran 77. However, these burde ..."
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Cited by 4 (2 self)
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Array programming languages such as Fortran 90, High Performance Fortran and ZPL are well-suited to scientic computing because they free the scientist from the responsibility of managing burdensome low-level details that complicate programming in languages like C and Fortran 77. However, these burdensome details are critical to performance, thus necessitating aggressive compilation techniques for their optimization. In this paper, we present a new compiler optimization called Array Subexpression Elimination (ASE) that lets a programmer take advantage of the expressibility aorded by array languages and achieve enviable portability and performance. We design a set of micro-benchmarks that model an important class of computations known as stencils and we report on our implementation of this optimization in the context of this micro-benchmark suite. Our results include a 125% improvement on one of these benchmarks and a 50% average speedup across the suite. Also we show a speedup of 32% improvement on the ZPL port of the NAS MG Parallel Benchmark and a 29% speedup over the handoptimized Fortran version. Further, the compilation time is only negligibly aected.
A pragmatic approach to compilation of Erlang
, 1997
"... Erlang is a functional language used in telecommunication products that may contain several hundred thousand lines of source code. In these real-world applications, high runtime performance must be combined with small object-code size and short compilation times. We solve this problem by extendi ..."
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Cited by 2 (1 self)
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Erlang is a functional language used in telecommunication products that may contain several hundred thousand lines of source code. In these real-world applications, high runtime performance must be combined with small object-code size and short compilation times. We solve this problem by extending a bytecode implementation of Erlang with a backend compiler that selectively compiles individual functions from their bytecode representation to native code. We discuss how stack-based bytecode is compiled to register code and how the bytecode and native code execution environments are integrated.
Optimal bitwise register allocation using integer linear programming
- In International Workshop on Languages and Compilers for Parallel Computing (LCPC’06), LNCS
, 2006
"... Abstract. This paper addresses the problem of optimal global register allocation. The register allocation problem is expressed as an integer linear programming problem and solved optimally. The model is more flexible than previous graphcoloring based methods and thus allows for register allocations ..."
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Cited by 2 (0 self)
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Abstract. This paper addresses the problem of optimal global register allocation. The register allocation problem is expressed as an integer linear programming problem and solved optimally. The model is more flexible than previous graphcoloring based methods and thus allows for register allocations with significantly fewer moves and spills. The formulation can also model complex architectural features, such as bit-wise access to registers. With bit-wise access to registers, multiple subword temporaries can be stored in a single register and accessed efficiently, resulting in a register allocation problem that cannot be addressed effectively with simple graph coloring. The paper describes techniques that can help reduce the problem size of the ILP formulation, making the algorithm feasible in practice. Preliminary empirical results from an implementation prototype are reported. 1
Formal Compiler Implementation in a Logical Framework
- In MERλIN, Second ACM SIGPLAN Workshop on
, 2003
"... The task of designing and implementing a compiler can be a difficult and error-prone process. In this paper, we present a new approach based on the use of higher-order abstract syntax and term rewriting in a logical framework. All program transformations, from parsing to code generation, are cleanly ..."
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Cited by 1 (1 self)
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The task of designing and implementing a compiler can be a difficult and error-prone process. In this paper, we present a new approach based on the use of higher-order abstract syntax and term rewriting in a logical framework. All program transformations, from parsing to code generation, are cleanly isolated and specified as term rewrites. This has several advantages. The correctness of the compiler depends solely on a small set of rewrite rules that are written in the language of formal mathematics. In addition, the logical framework guarantees the preservation of scoping, and it automates many frequently-occurring tasks including substitution and rewriting strategies. As we show, compiler development in a logical framework can be easier than in a general-purpose language like ML, in part because of automation, and also because the framework provides extensive support for examination, validation, and debugging of the compiler transformations. The paper is organized around a case study, using the MetaPRL logical framework to compile an ML-like language to Intel x86 assembly. We also present a scoped formalization of x86 assembly in which all registers are immutable.
Mapping and performance evaluation for heterogeneous MP-SoCs via packing
- In Proc. International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS’07
, 2007
"... Abstract. The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to tackle this demand. But to be able to take advantage of the benefits of these systems, new strategies are required how to map applicat ..."
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Cited by 1 (1 self)
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Abstract. The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to tackle this demand. But to be able to take advantage of the benefits of these systems, new strategies are required how to map applications to such a system and how to evaluate the system’s performance at a very early design stage. We will present a static, analytical, bottom-up methodology for temporal and spatial mapping of applications to MP-SoCs based on packing. Furthermore we will demonstrate how the result can be used for performance evaluation and system improvement without the need for simulations. 1

